LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 624
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
- LPC1767FBD100551 PDF datasheet #2
- LPC1767FBD100551 PDF datasheet #3
- LPC1769FBD100551 PDF datasheet #4
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NXP Semiconductors
UM10360
User manual
32.7.2 Set Baud Rate <Baud Rate> <stop bit>
32.7.3 Echo <setting>
32.7.4 Write to RAM <start address> <number of bytes>
Table 572. ISP Set Baud Rate command
Table 573. Correlation between possible ISP baudrates and CCLK frequency (in MHz)
[1]
Table 574. ISP Echo command
The host should send the data only after receiving the CMD_SUCCESS return code. The
host should send the check-sum after transmitting 20 UU-encoded lines. The checksum is
generated by adding raw data (before UU-encoding) bytes and is reset after transmitting
20 UU-encoded lines. The length of any UU-encoded line should not exceed
61 characters (bytes) i.e. it can hold 45 data bytes. When the data fits in less than
20 UU-encoded lines then the check-sum should be of the actual number of bytes sent.
Command
Input
Return Code
Description
Example
ISP Baudrate .vs.
CCLK Frequency
10.0000
11.0592
12.2880
14.7456
15.3600
18.4320
19.6608
24.5760
25.0000
Command
Input
Return Code
Description
Example
ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK = 14.748 MHz
[1]
B
Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400
Stop bit: 1 | 2
CMD_SUCCESS |
INVALID_BAUD_RATE |
INVALID_STOP_BIT |
PARAM_ERROR
This command is used to change the baud rate. The new baud rate is effective
after the command handler sends the CMD_SUCCESS return code.
"B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit.
A
Setting: ON = 1 | OFF = 0
CMD_SUCCESS |
PARAM_ERROR
The default setting for echo command is ON. When ON the ISP command handler
sends the received serial data back to the host.
"A 0<CR><LF>" turns echo off.
All information provided in this document is subject to legal disclaimers.
Chapter 32: LPC17xx Flash memory interface and programming
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UM10360
© NXP B.V. 2010. All rights reserved.
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