LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 607

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
31.6 Using the DMA controller
UM10360
User manual
31.6.1.1 Enabling the DMA controller
31.6.1.2 Disabling the DMA controller
31.6.1.3 Enabling a DMA channel
31.6.1.4 Disabling a DMA channel
31.6.1.5 Setting up a new DMA transfer
31.6.1 Programming the DMA controller
All accesses to the DMA Controller internal register must be word (32-bit) reads and
writes.
To enable the DMA controller set the Enable bit in the DMACConfig register.
To disable the DMA controller:
To enable the DMA channel set the channel enable bit in the relevant DMA channel
configuration register. Note that the channel must be fully initialized before it is enabled.
A DMA channel can be disabled in three ways:
Disabling a DMA channel and losing data in the FIFO
Clear the relevant channel enable bit in the relevant channel configuration register. The
current AHB transfer (if one is in progress) completes and the channel is disabled. Any
data in the FIFO is lost.
Disabling the DMA channel without losing data in the FIFO
To set up a new DMA transfer:
If the channel is not set aside for the DMA transaction:
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Read the DMACEnbldChns register and ensure that all the DMA channels have been
disabled. If any channels are active, see Disabling a DMA channel.
Disable the DMA controller by writing 0 to the DMA Enable bit in the DMACConfig
register.
By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost
if this method is used.
By using the active and halt bits in conjunction with the channel enable bit.
By waiting until the transfer completes. This automatically clears the channel.
Set the halt bit in the relevant channel configuration register. This causes any future
DMA request to be ignored.
Poll the active bit in the relevant channel configuration register until it reaches 0. This
bit indicates whether there is any data in the channel that has to be transferred.
Clear the channel enable bit in the relevant channel configuration register
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
UM10360
© NXP B.V. 2010. All rights reserved.
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