LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 92

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 72.
UM10360
User manual
Pin Symbol
Row A
1
5
9
Row B
1
5
9
Row C
1
5
9
Row D
1
5
9
Row E
1
TDO/SWO
P1[10]/ENET_RXD1
P0[7]/I2STX_CLK/
SCK1/MAT2[1]
TMS/SWDIO
P1[9]/ENET_RXD0
P2[0]/PWM1[1]/TXD1
TCK/SWDCLK
P1[8]/ENET_CRS
V
P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
P1[0]/ENET_TXD0
P2[4]/PWM1[5]/
DSR1/TRACEDATA[1]
V
SS
SSA
Pin allocation table TFBGA100 package
Fig 16. Pin configuration TFBGA100 package
Pin Symbol
2
6
10
2
6
10
2
6
10
2
6
10
2
P0[3]/RXD0/AD0[6]
P1[16]/ENET_MDC
P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
RTCK
P1[17]/
ENET_MDIO
P2[1]/PWM1[2]/RXD1
TRST
P1[15]/
ENET_REF_CLK
V
P0[25]/AD0[2]/
I2SRX_SDA/TXD3
P1[14]/ENET_RX_ER
P2[5]/PWM1[6]/
DTR1/TRACEDATA[0]
V
DD(3V3)
DDA
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
ball A1
index area
G
A
B
C
D
E
H
K
F
J
Pin Symbol
3
7
11
3
7
11
3
7
11
3
7
11
3
1
2
V
V
-
V
V
-
TDI
P4[28]/RX_MCLK/
MAT2[0]/TXD3
-
P0[26]/AD0[3]/
AOUT/RXD3
P0[5]/I2SRX_WS/
TD2/CAP2[1]
-
VREFP
DD(3V3)
DD(REG)(3V3)
SS
SS
3
Transparent top view
LPC1768FET100
4
5
Chapter 7: LPC17xx Pin configuration
6
7
8
9
002aaf723
10
Pin Symbol
4
8
12
4
8
12
4
8
12
4
8
12
4
P1[4]/ENET_TX_EN
P0[4]/I2SRX_CLK/
RD2/CAP2[0]
-
P1[1]/ENET_TXD1
P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
-
P0[2]/TXD0/AD0[7]
P0[8]/I2STX_WS/
MISO1/MAT2[2]
-
n.c.
P2[2]/PWM1[3]/
CTS1/TRACEDATA[3]
-
n.c.
UM10360
© NXP B.V. 2010. All rights reserved.
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