LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 753

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 641. Faults
[1]
[2]
UM10360
User manual
Fault
Bus error on a vector read
Fault escalated to a hard fault
MPU mismatch:
Bus error:
Precise data bus error
Imprecise data bus error
Attempt to access a coprocessor
Undefined instruction
Attempt to enter an invalid instruction set state
Invalid EXC_RETURN value
Illegal unaligned load or store
Divide By 0
Occurs on an access to an XN region even if the MPU is disabled.
Attempting to use an instruction set other than the Thumb instruction set.
34.3.4.1 Fault types
34.3.4 Fault handling
on instruction access
on data access
during exception stacking
during exception unstacking
during exception stacking
during exception unstacking
during instruction prefetch
Faults are a subset of the exceptions, see
Table 641
status register, and the register bit that indicates that the fault has occurred. See
Section 34.4.3.11 “Configurable Fault Status Register”
status registers.
•
•
•
•
a bus error on:
– an instruction fetch or vector table load
– a data access
an internally-detected error such as an undefined instruction or an attempt to change
state with a BX instruction
attempting to execute an instruction from a memory region marked as
Non-Executable (XN)
an MPU fault because of a privilege violation or an attempt to access an unmanaged
region
shows the types of fault, the handler used for the fault, the corresponding fault
All information provided in this document is subject to legal disclaimers.
[2]
Rev. 2 — 19 August 2010
Handler
Hard fault
Memory
management
fault
Bus fault
Usage fault
Bit name
VECTTBL
FORCED
-
IACCVIOL
DACCVIOL
MSTKERR
MUNSKERR
-
STKERR
UNSTKERR
IBUSERR
PRECISERR
IMPRECISERR
NOCP
UNDEFINSTR
INVSTATE
INVPC
UNALIGNED
DIVBYZERO
Chapter 34: Appendix: Cortex-M3 user guide
Section
[1]
34.3.3. The following generate a fault:
for more information about the fault
Fault status register
Section 34.4.3.12 “Hard Fault
Status Register”
-
Section 34.4.3.13 “Memory
Management Fault Address
Register”
-
Section 34.4.3.14 “Bus Fault
Address Register”
Section 34.4.3.11.3 “Usage Fault
Status Register”
UM10360
© NXP B.V. 2010. All rights reserved.
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