LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 739

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.3.2.3 Behavior of memory accesses
34.3.2.4 Software ordering of memory accesses
The behavior of accesses to each region in the memory map is:
Table 635.
[1]
The Code, SRAM, and external RAM regions can hold programs. However, the most
efficient access to programs is from the Code region. This is because the processor has
separate buses that enable instruction fetches and data accesses to occur
simultaneously.
The MPU can override the default memory access behavior described in this section. For
more information, see
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions. This is because:
Section 34.3.2.2
memory accesses. Otherwise, if the order of memory accesses is critical, software must
include memory barrier instructions to force that ordering. The processor provides the
following memory barrier instructions:
Address
range
0x00000000 -
0x1FFFFFFF
0x20000000 -
0x3FFFFFFF
0x40000000 -
0x5FFFFFFF
0x60000000 -
0x9FFFFFFF
0xA0000000 -
0xDFFFFFFF
0xE0000000 -
0xE00FFFFF
0xE0100000 -
0xFFFFFFFF
•
•
•
•
‘<‘ means that accesses are observed in program order, that is, A1 is always observed
before A2.
See
the processor can reorder some memory accesses to improve efficiency, providing
this does not affect the behavior of the instruction sequence.
the processor has multiple bus interfaces
memory or devices in the memory map have different wait states
some memory accesses are buffered or speculative.
Section 34.3.2.1
Memory access behavior
Memory
region
Code
SRAM
Peripheral
External
RAM
External
device
Private Peripheral
Bus
Vendor-
specific device
All information provided in this document is subject to legal disclaimers.
describes the cases where the memory system guarantees the order of
for more information.
Section 34.4.5 “Memory protection
Rev. 2 — 19 August 2010
Memory
type
Normal
Normal
Device
Normal
Device
Strongly-
ordered
Device
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Chapter 34: Appendix: Cortex-M3 user guide
XN
-
-
XN
-
XN
XN
XN
[1]
[1]
[1]
[1]
Description
Executable region for program code.
You can also put data here.
Executable region for data. You can
also put code here.
This region includes bit band and bit
band alias areas, see
This region includes bit band and bit
band alias areas, see
Executable region for data.
External Device memory
This region includes the NVIC, System
timer, and system control block.
Not used for NXP devices.
unit”.
UM10360
© NXP B.V. 2010. All rights reserved.
Table
Table
636.
637.
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