LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 282

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
13.8.12 I
13.8.11 I
Table 263. I
This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.
The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure
occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored.
I2C_TX must be written for both write and read operations to transfer each byte. Bits [7:0]
are ignored for master-receive operations. The master-receiver must write a dummy byte
to the TX FIFO for each byte it expects to receive in the RX FIFO. When the STOP bit is
set or the START bit is set to cause a RESTART condition on a byte written to the TX
FIFO (master-receiver), then the byte read from the slave is not acknowledged. That is,
the last byte of a master-receive operation is not acknowledged.
Table 264. I
The I2C_STS register provides status information on the TX and RX blocks as well as the
current state of the external buses. Individual bits are enabled as interrupts by the
I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt.
Table 265. I
Bit
7:0
Bit
7:0
8
9
31:10 -
Bit
0
1
2
2
C Transmit Register (I2C_TX - 0x5000 C300)
C Status Register (I2C_STS - 0x5000 C304)
Symbol
RX Data
Symbol Value Description
TDI
AFI
Symbol
TX Data
START
STOP
2
2
2
C Receive register (I2C_RX - address 0x5000 C300) bit description
C Transmit register (I2C_TX - address 0x5000 C300) bit description
C status register (I2C_STS - address 0x5000 C304) bit description
All information provided in this document is subject to legal disclaimers.
0
1
0
1
When 1, issue a STOP condition after transmitting this byte.
Description
Transmit data.
When 1, issue a START condition before transmitting this byte.
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Transaction Done Interrupt. This flag is set if a transaction
completes successfully. It is cleared by writing a one to bit 0 of
the status register. It is unaffected by slave transactions.
Transaction has not completed.
Transaction completed.
Arbitration Failure Interrupt. When transmitting, if the SDA is low
when SDAOUT is high, then this I
another device on the bus. The Arbitration Failure bit is set when
this happens. It is cleared by writing a one to bit 1 of the status
register.
No arbitration failure on last transmission.
Arbitration failure occurred on last transmission.
Description
Receive data.
2
C has lost the arbitration to
Chapter 13: LPC17xx USB OTG
UM10360
© NXP B.V. 2010. All rights reserved.
282 of 840
Reset
Value
-
-
-
-
Reset
Value
0
0
Reset
Value
-