LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 8

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
1.5 Simplified block diagram
UM10360
User manual
Fig 1.
LPC1768 simplified block diagram
oscillator
32 kHz
High Speed GPIO
RTC Power Domain
APB slave group 0
20 bytes of backup
Pin Connect Block
GPIO Interrupt Ctl
Capture/Compare
Watchdog Timer
Real Time Clock
UARTs 0 & 1
Timers 0 & 1
12-bit ADC
CAN 1 & 2
I
registers
2
PWM1
C 0 & 1
SSP1
SPI0
Trace
Port
ARM Cortex-M3
Test/Debug Interface
All information provided in this document is subject to legal disclaimers.
interface
JTAG
APB bridge
AHB to
Rev. 2 — 19 August 2010
Multilayer AHB Matrix
controller
DMA
APB bridge
AHB to
Ethernet
interface
Ethernet
10/100
Chapter 1: LPC17xx Introductory information
MAC
PHY
interface
Note: shaded peripheral blocks
support General Purpose DMA
device,
USB
USB
host,
OTG
Quadrature Encoder
APB slave group 1
Motor Control PWM
Repetitive Interrupt
External Interrupts
Capture/Compare
System Control
UARTs 2 & 3
Timers 2 & 3
Controls
Clocks
SSP0
Timer
and
Accelerator
DAC
I
SRAM
I2S
64 kB
2
ROM
8 kB
C2
Flash
Clock Generation,
Brownout Detect,
system functions
Power Control,
and other
UM10360
© NXP B.V. 2010. All rights reserved.
512 kB
Flash
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