LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 440
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 383. I
[1]
UM10360
User manual
Generic
Name
I2ADR2
I2ADR3
I2DATA_
BUFFER
I2MASK0
I2MASK1
I2MASK2
I2MASK3
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
2
C register map
Description
I2C Slave Address Register 2. Contains the 7-bit
slave address for operation of the I
slave mode, and is not used in master mode. The
least significant bit determines whether a slave
responds to the General Call address.
I2C Slave Address Register 3. Contains the 7-bit
slave address for operation of the I
slave mode, and is not used in master mode. The
least significant bit determines whether a slave
responds to the General Call address.
Data buffer register. The contents of the 8 MSBs of
the I2DAT shift register will be transferred to the
I2DATA_BUFFER automatically after every 9 bits (8
bits of data plus ACK or NACK) has been received
on the bus.
I2C Slave address mask register 0 . This mask
register is associated with I2ADR0 to determine an
address match. The mask register has no effect
when comparing to the General Call address
(‘0000000’).
I2C Slave address mask register 1 . This mask
register is associated with I2ADR0 to determine an
address match. The mask register has no effect
when comparing to the General Call address
(‘0000000’).
I2C Slave address mask register 2 . This mask
register is associated with I2ADR0 to determine an
address match. The mask register has no effect
when comparing to the General Call address
(‘0000000’).
I2C Slave address mask register 3 . This mask
register is associated with I2ADR0 to determine an
address match. The mask register has no effect
when comparing to the General Call address
(‘0000000’).
19.8.1 I
0x4001 C000; I
0x400A 0000)
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Reading this register provides the current values of the control and flag bits.
2
C Control Set register (I2CONSET: I
All information provided in this document is subject to legal disclaimers.
2
C interface. Writing a one to a bit of this register causes the
2
C1, I2C1CONSET - 0x4005 C000; I
2
2
C interface in
C interface in
Rev. 2 — 19 August 2010
2
C control register to be set. Writing a zero has no effect.
Access Reset
R/W
R/W
RO
R/W
R/W
R/W
R/W
value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
2
C0, I2C0CONSET -
[1]
I
I2C0ADR2 - 0x4001 C024
I2C1ADR2 - 0x4005 C024
I2C2ADR2 - 0x400A 0024
I2C0ADR3 - 0x4001 C028
I2C1ADR3 - 0x4005 C028
I2C2ADR3 - 0x400A 0028
I2C0DATA_ BUFFER - 0x4001 C02C
I2C1DATA_ BUFFER - 0x4005 C02C
I2C2DATA_ BUFFER - 0x400A 002C
I2C0MASK0 - 0x4001 C030
I2C1MASK0 - 0x4005 C030
I2C2MASK0 - 0x400A 0030
I2C0MASK1 - 0x4001 C034
I2C1MASK1 - 0x4005 C034
I2C2MASK1 - 0x400A 0034
I2C0MASK2 - 0x4001 C038
I2C1MASK2 - 0x4005 C038
I2C2MASK2 - 0x400A 0038
I2C0MASK3 - 0x4001 C03C
I2C1MASK3 - 0x4005 C03C
I2C2MASK3 - 0x400A 003C
2
Cn Name & Address
Chapter 19: LPC17xx I2C0/1/2
2
C2, I2C2CONSET -
UM10360
© NXP B.V. 2010. All rights reserved.
440 of 840
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