LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 582

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

30.1 Basic configuration
30.2 Features
30.3 Pin description
Table 537. D/A Pin Description
UM10360
User manual
Pin
AOUT
V
V
REFP
DDA
, V
, V
SSA
REFN
Type
Output
Reference
Power
The DAC is configured using the following registers:
Table 537
1. Power: The DAC is always connected to V
2. Clock: In the PCLKSEL0 register
3. Pins: Enable the DAC pin through the PINSEL registers. Select pin mode for port pin
4. DMA: The DAC can be connected to the GPDMA controller (see
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•
•
•
•
•
UM10360
Chapter 30: LPC17xx Digital-to-Analog Converter (DAC)
Rev. 2 — 19 August 2010
PINSEL and PINMODE settings (see below).
with DAC through the PINMODE registers
accessing any DAC registers.
GPDMA connections, see
10-bit digital to analog converter
Resistor string architecture
Buffered output
Power-down mode
Selectable speed vs. power
Maximum update rate of 1 MHz.
Description
Analog Output. After the selected settling time after the DACR is written with a new value,
the voltage on this pin (with respect to V
Voltage References. These pins provide a voltage reference level for the ADC and DAC.
Note: V
DAC are not used.
Analog Power and Ground. These should typically be the same voltages as V
but should be isolated to minimize noise and error. Note: VDDA should be tied to VDD(3V3)
and VSSA should be tied to VSS if the ADC and DAC are not used.
gives a brief summary of each of DAC related pins.
REFP
All information provided in this document is subject to legal disclaimers.
should be tied to VDD(3V3) and V
Rev. 2 — 19 August 2010
Table
543.
(Table
SSA
) is VALUE × ((V
40), select PCLK_DAC.
DDA
(Section
REFN
. Register access is determined by
should be tied to V
8.5). This must be done before
REFP
- V
REFN
Section
)/1024) + V
© NXP B.V. 2010. All rights reserved.
SS
if the ADC and
User manual
DD
30.4.2). For
and V
REFN
582 of 840
SS
.
,