LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 26

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
3.6.4 External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)
Table 11.
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function Only pins that are
selected for the EINT function (see
register) can cause interrupts from the External Interrupt function (though of course pins
selected for other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write
the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the
interrupt. An extraneous interrupt(s) could be set by changing the polarity and not
having the EXTINT cleared.
Table 12.
Bit
0
1
2
3
31:4 -
Bit
0
1
2
Symbol
EXTPOLAR0 0
EXTPOLAR1 0
EXTPOLAR2 0
Symbol
EXTMODE0
EXTMODE1
EXTMODE2
EXTMODE3
External Interrupt Mode register (EXTMODE - address 0x400F C148) bit
description
External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
-
Value Description
1
1
1
Rev. 2 — 19 August 2010
Level-sensitivity is selected for EINT0.
EINT0 is edge sensitive.
Level-sensitivity is selected for EINT1.
EINT1 is edge sensitive.
Level-sensitivity is selected for EINT2.
EINT2 is edge sensitive.
Level-sensitivity is selected for EINT3.
EINT3 is edge sensitive.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
EINT0 is low-active or falling-edge sensitive (depending on
EXTMODE0).
EINT0 is high-active or rising-edge sensitive (depending on
EXTMODE0).
EINT1 is low-active or falling-edge sensitive (depending on
EXTMODE1).
EINT1 is high-active or rising-edge sensitive (depending on
EXTMODE1).
EINT2 is low-active or falling-edge sensitive (depending on
EXTMODE2).
EINT2 is high-active or rising-edge sensitive (depending on
EXTMODE2).
Section
8.5) and enabled in the appropriate NVIC
Chapter 3: LPC17xx System control
UM10360
© NXP B.V. 2010. All rights reserved.
26 of 840
Reset
value
0
0
0
0
NA
Reset
value
0
0
0