LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 386
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
16.16.2.1 FullCAN message interrupt enable bit
16.16.2 FullCAN interrupts
The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a
maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM
is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured to
participate in the interrupt scheme. It is still possible to define more than 64 FullCAN
objects. The only difference is, that the remaining FullCAN objects will not provide a
FullCAN interrupt.
The FullCAN Interrupt Register-set contains interrupt flags (IntPndx) for (pending)
FullCAN receive interrupts. As soon as a FullCAN message is received, the according
interrupt bit (IntPndx) in the FCAN Interrupt Register gets asserted. In case that the Global
FullCAN Interrupt Enable bit is set, the FullCAN Receive Interrupt is passed to the
Vectored Interrupt Controller.
Application Software has to solve the following:
The software that covers the interrupt priority handling has to assign a receive interrupt
priority to every FullCAN object. If more than one interrupt is pending, then the software
has to decide, which received FullCAN object has to be served next.
To each FullCAN object a new FullCAN Interrupt Enable bit (FCANIntxEn) is added, so
that it is possible to enable or disable FullCAN interrupts for each object individually. The
new Message Lost flag (MsgLstx) is introduced to indicate whether more than one
FullCAN message has been received since last time this message object was read by the
CPU. The Interrupt Enable and the Message Lost bits reside in the existing Look-up Table
RAM.
In
FullCAN, Section. The new introduced FullCAN Message Interrupt enable bit can be used
to enable for each FullCAN message an Interrupt.
1. Index/Object number calculation based on the bit position in the FCANIC Interrupt
2. Interrupt priority handling if more than one FullCAN receive interrupt is pending.
Figure 63
Register for more than one pending interrupt.
8 FullCAN Identifiers with their Source CAN Channel are defined in the
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
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