LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 532
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 469. MCPWM Count Control read address (MCCNTCON - 0x400B 805C) bit description
Table 470. MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060) bit description
Table 471. MCPWM Count Control clear address (MCCAPCON_CLR - 0x400B 8064) bit description
UM10360
User manual
Bit
13
14
15
16
17
28:18 -
29
30
31
Bit
31:0
Bit
31:0
Symbol
TC2MCI0_FE
TC2MCI1_RE
TC2MCI1_FE
TC2MCI2_RE
TC2MCI2_FE
CNTR0
CNTR1
CNTR2
Description
Writing one(s) to this write-only address sets the corresponding bit(s) in the MCCNTCON register. See
Description
Writing one(s) to this write-only address clears the corresponding bit(s) in the MCCNTCON register. See
Table
25.7.4.2 MCPWM Count Control set address (MCCNTCON_SET - 0x400B 8060)
25.7.4.3 MCPWM Count Control clear address (MCCNTCON_CLR - 0x400B 8064)
25.7.5 MCPWM Timer/Counter 0-2 registers (MCTC0-2 - 0x400B 8018,
469.
Writing one(s) to this write-only address sets the corresponding bit(s) in MCCNTCON.
Writing one(s) to this write-only address clears the corresponding bit(s) in MCCNTCON.
0x400B 801C, 0x400B 8020)
These registers hold the current values of the 32-bit counter/timers for channels 0-2. Each
value is incremented on every PCLK, or by edges on the MCI0-2 pins, as selected by
MCCNTCON. The timer/counter counts up from 0 until it reaches the value in its
corresponding MCPER register (or is stopped by writing to MCCON_CLR).
A TC register can be read at any time. In order to write to the TC register, its channel must
be stopped. If not, the write will not take place, no exception is generated.
Value Description
1
0
1
0
1
0
1
0
1
0
-
1
0
1
0
1
0
If MODE2 is 1, counter 2 advances on a falling edge on MCI0.
A falling edge on MCI0 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a rising edge on MCI1.
A rising edge on MCI1 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a falling edge on MCI1.
A falling edge on MCI1 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a rising edge on MCI2.
A rising edge on MCI2 does not affect counter 2.
If MODE2 is 1, counter 2 advances on a falling edge on MCI2.
A falling edge on MCI2 does not affect counter 2.
Reserved.
Channel 0 is in counter mode.
Channel 0 is in timer mode.
Channel 1 is in counter mode.
Channel 1 is in timer mode.
Channel 2 is in counter mode.
Channel 2 is in timer mode.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 25: LPC17xx Motor control PWM
UM10360
© NXP B.V. 2010. All rights reserved.
Table
532 of 840
0
0
0
0
0
0
0
0
Reset
Value
-
469.
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