LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 37

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
4.5.4 PLL0 Configuration register (PLL0CFG - 0x400F C084)
output clock. Changes to the PLL0CON register do not take effect until a correct PLL0
feed sequence has been given (see
0x400F
Table 19.
PLL0 must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL0 output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that PLL0 is locked before it is connected or automatically
disconnect PLL0 if lock is lost during operation. In the event of loss of lock on PLL0, it is
likely that the oscillator clock has become unstable and disconnecting PLL0 will not
remedy the situation.
The PLL0CFG register contains PLL0 multiplier and divider values. Changes to the
PLL0CFG register do not take effect until a correct PLL feed sequence has been given
(see
the PLL frequency, and multiplier and divider values are found in the
frequency
Table 20.
Bit
0
1
31:2
Bit
14:0
15
23:16 NSEL0
31:24 -
Section 4.5.8 “PLL0 Feed register (PLL0FEED - 0x400F
Symbol
PLLE0
PLLC0
-
Symbol
MSEL0
-
C08C)”).
calculation”.
PLL Control register (PLL0CON - address 0x400F C080) bit description
PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description
All information provided in this document is subject to legal disclaimers.
Description
PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate
PLL0 and allow it to lock to the requested frequency. See PLL0STAT
register,
PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and
locked, then followed by a valid PLL0 feed sequence causes PLL0 to
become the clock source for the CPU, AHB peripherals, and used to
derive the clocks for APB peripherals. The PLL0 output may potentially
be used to clock the USB subsystem if the frequency is 48 MHz. See
PLL0STAT register,
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
PLL0 Multiplier value. Supplies the value "M" in PLL0 frequency
calculations. The value stored here is M - 1. Supported values for M
are 6 through 512 and those listed in
Note: Not all values of M are needed, and therefore some are not
supported by hardware. For details on selecting values for MSEL0 see
Section 4.5.10 “PLL0 frequency
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
PLL0 Pre-Divider value. Supplies the value "N" in PLL0 frequency
calculations. The value stored here is N - 1. Supported values for N are
1 through 32.
Note: For details on selecting the right value for NSEL0 see
Section 4.5.10 “PLL0 frequency
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Table
22.
Table
Section 4.5.8 “PLL0 Feed register (PLL0FEED -
Chapter 4: LPC17xx Clocking and power control
22.
calculation”.
calculation”.
Table
21.
C08C)”). Calculations for
Section 4.5.10 “PLL0
UM10360
© NXP B.V. 2010. All rights reserved.
37 of 840
Reset
value
0
0
NA
Reset
value
0
NA
0
NA