LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 154

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 137. Test register (TEST - address 0x5000 ) bit description
Table 138. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description
UM10360
User manual
Bit
0
1
2
31:3
Bit
0
1
5:2
14:6
15
31:16
Symbol
SHORTCUT PAUSE
QUANTA
TEST PAUSE
TEST
BACKPRESSURE
-
Symbol
SCAN INCREMENT
SUPPRESS
PREAMBLE
CLOCK SELECT
-
RESET MII MGMT
-
10.11.9 MII Mgmt Configuration Register (MCFG - 0x5000 0020)
The MII Mgmt Configuration register (MCFG) has an address of 0x5000 0020. The bit
definition of this register is shown in
Table 139. Clock select encoding
Clock Select
Host Clock divided by 4
Host Clock divided by 6
Host Clock divided by 8
Host Clock divided by 10
Host Clock divided by 14
Host Clock divided by 20
Host Clock divided by 28
Host Clock divided by 36
Host Clock divided by 40
Host Clock divided by 44
Function
This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.
This bit causes the MAC Control sublayer to inhibit transmissions, just as if a
PAUSE Receive Control frame with a nonzero pause time parameter was received.
Setting this bit will cause the MAC to assert backpressure on the link. Backpressure
causes preamble to be transmitted, raising carrier sense. A transmit packet from the
system will be sent during backpressure.
Unused
Function
Set this bit to cause the MII Management hardware to perform read cycles across a
range of PHYs. When set, the MII Management hardware will perform read cycles
from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow
continuous reads of the same PHY.
Set this bit to cause the MII Management hardware to perform read/write cycles
without the 32-bit preamble field. Clear this bit to cause normal cycles to be
performed. Some PHYs support suppressed preamble.
This field is used by the clock divide logic in creating the MII Management Clock
(MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs
support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided
by the specified amount. Refer to
field.
Unused
This bit resets the MII Management hardware.
Unused
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Bit 5
0
0
0
0
0
0
0
1
1
1
Bit 4
0
0
0
1
1
1
1
0
0
0
Table 139
Table
138.
Bit 3
0
1
1
0
0
1
1
0
0
1
below for the definition of values for this
Bit 2
x
0
1
0
1
0
1
0
1
0
Chapter 10: LPC17xx Ethernet
Maximum AHB
clock supported
10
15
20
25
35
50
70
80
90
100
[1]
[1]
[1]
UM10360
© NXP B.V. 2010. All rights reserved.
154 of 840
Reset
value
0
0x0
Reset
value
0
0
0
0x0
0
0x0
0
0