LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 61
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
4.8.7 Power Mode Control register (PCON - 0x400F C0C0)
Controls for some reduced power modes and other power related controls are contained
in the PCON register, as described in
Table 44.
[1]
[2]
[3]
Bit
0
1
2
3
4
7:3
8
9
10
11
31:12 -
Only one of these flags will be valid at a specific time.
Hardware reset only for a power-up of core power or by a brownout detect event.
Hardware reset only for a power-up event on Vbat.
Symbol
PM0
PM1
BODRPM Brown-Out Reduced Power Mode. When BODRPM is 1, the
BOGD
BORD
-
SMFLAG
DSFLAG
PDFLAG
DPDFLAG Deep Power-down entry flag. Set when the Deep Power-down mode
Power Mode Control register (PCON - address 0x400F C0C0) bit description
All information provided in this document is subject to legal disclaimers.
Description
Power mode control bit 0. This bit controls entry to the Power-down
mode. See
Power mode control bit 1. This bit controls entry to the Deep
Power-down mode. See
Brown-Out Detect circuitry will be turned off when chip Power-down
mode or Deep Sleep mode is entered, resulting in a further reduction
in power usage. However, the possibility of using Brown-Out Detect as
a wake-up source from the reduced power mode will be lost.
When 0, the Brown-Out Detect function remains active during
Power-down and Deep Sleep modes.
See the System Control Block chapter for details of Brown-Out
detection.
Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect
circuitry is fully disabled at all times, and does not consume power.
When 0, the Brown-Out Detect circuitry is enabled.
See the System Control Block chapter for details of Brown-Out
detection.
Brown-Out Reset Disable. When BORD is 1, the BOD will not reset
the device when the V
reset trip level. The Brown-Out interrupt is not affected.
When BORD is 0, the BOD reset is enabled.
See the
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Sleep Mode entry flag. Set when the Sleep mode is successfully
entered. Cleared by software writing a one to this bit.
Deep Sleep entry flag. Set when the Deep Sleep mode is successfully
entered. Cleared by software writing a one to this bit.
Power-down entry flag. Set when the Power-down mode is
successfully entered. Cleared by software writing a one to this bit.
is successfully entered. Cleared by software writing a one to this bit.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Section 3.5
Section 4.8.7.1
for details of Brown-Out detection.
Chapter 4: LPC17xx Clocking and power control
Table
DD(REG)(3V3)
Section 4.8.7.1
below for details.
44.
voltage dips goes below the BOD
below for details.
UM10360
© NXP B.V. 2010. All rights reserved.
61 of 840
Reset
value
0
0
0
0
0
NA
0
0
0
0
NA
[1][2]
[1][2]
[1][2]
[1][3]
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