LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 657

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.2.3.7.1 The condition flags
34.2.3.7.2 Condition code suffixes
Use the CBZ and CBNZ instructions to compare the value of a register against zero and
branch on the result.
This section describes:
The APSR contains the following condition flags:
N — Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z — Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C — Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V — Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR see
A carry occurs:
Overflow occurs if the result of an add, subtract, or compare is greater than or equal to
2
Remark: Most instructions update the status flags only if the S suffix is specified. See the
instruction descriptions for more information.
The instructions that can be conditional have an optional condition code, shown in syntax
descriptions as {cond}. Conditional execution requires a preceding IT instruction. An
instruction with a condition code is only executed if the condition code flags in the APSR
meet the specified condition.
You can use conditional execution with the IT instruction to reduce the number of branch
instructions in code.
Table 615
and V flags.
Table 615. Condition code suffixes
Suffix
EQ
NE
CS or HS
CC or LO
MI
31
•
•
•
•
•
, or less than –2
Section 34.2.3.7.1 “The condition flags”
Section 34.2.3.7.2 “Condition code
if the result of an addition is greater than or equal to 2
if the result of a subtraction is positive or zero
as the result of an inline barrel shifter operation in a move or logical instruction.
also shows the relationship between condition code suffixes and the N, Z, C,
All information provided in this document is subject to legal disclaimers.
Flags
Z = 1
Z = 0
C = 1
C = 0
N = 1
31
.
Rev. 2 — 19 August 2010
Table 615
Meaning
Equal
Not equal
Higher or same, unsigned ≥
Lower, unsigned <
Negative
suffixes”.
shows the condition codes to use.
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.3.1.3.5 “Program Status
32
UM10360
© NXP B.V. 2010. All rights reserved.
Register”.
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