LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 60

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
4.8.4 Deep Power-down mode
4.8.5 Peripheral power control
4.8.6 Register description
In Deep Power-down mode, power is shut off to the entire chip with the exception of the
Real-Time Clock, the RESET pin, the WIC, and the RTC backup registers. Entry to Deep
Power-down mode causes the DPDFLAG bit in PCON to be set, see
To optimize power conservation, the user has the additional option of turning off or
retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn
off power to the on-chip regulator via the V
Power-down mode.Power to the on-chip regulator must be restored before device
operation can be restarted.
Wake-up from Deep Power-down mode will occur when an external reset signal is
applied, or the RTC interrupt is enabled and an RTC interrupt is generated.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings. This is
detailed in the description of the PCONP register.
The Power Control function uses registers shown in
follow.
Table 43.
[1]
Name
PCON
PCONP
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Description
Power Control Register. This register contains
control bits that enable some reduced power
operating modes of the LPC17xx. See
Power Control for Peripherals Register. This
register contains control bits that enable and
disable individual peripheral functions, allowing
elimination of power consumption by peripherals
that are not needed.
Power Control registers
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 4: LPC17xx Clocking and power control
DD(REG)(3V3)
Table
44.
Table
pins after entering Deep
Access Reset
R/W
R/W
43. More detailed descriptions
value
0x00
Table
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
44.
Address
0x400F C0C0
0x400F C0C4
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