LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 465
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
19.9.8.1 Initialization
19.9.8.2 I
19.9.8.3 The state service routines
19.9.8.4 Adapting state services to an application
19.9.8 I
This section provides examples of operations that must be performed by various I
service routines. This includes:
In the initialization example, the I
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:
The I
Call. If the General Call or the own slave address is detected, an interrupt is requested
and I2STAT is loaded with the appropriate state information.
When the I
the 26 state services to be executed.
Each state routine is part of the I
The state service examples show the typical actions that must be performed in response
to the 26 I
associated state services can be omitted, as long as care is taken that the those states
can never occur.
In an application, it may be desirable to implement some kind of timeout during I
operations, in order to trap an inoperative bus or a lost service routine.
2
2
•
•
•
•
•
•
C interrupt service
C state service routines
Initialization of the I
I
The 26 state service routines providing support for all four I
The I2ADR registers and I2MASK registers are loaded with values to configure the
part’s own slave address(es) and the General Call bit (GC)
The I
The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON
and the serial clock frequency (for master modes) is defined by loading the
and I2SCLL registers.
2
2
C Interrupt Service
C hardware now begins checking the I
2
2
C interrupt enable and interrupt priority bits are set
2
C state codes. If one or more of the four I
C interrupt is entered, I2STAT contains a status code which identifies one of
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
2
The master routines must be started in the main program.
C block after a Reset.
2
2
C interrupt routine and handles one of the 26 states.
C block is enabled for both master and slave modes.
2
C-bus for its own slave address and General
2
C operating modes are not used, the
Chapter 19: LPC17xx I2C0/1/2
2
C operating modes.
UM10360
© NXP B.V. 2010. All rights reserved.
I2SCLH
2
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2
C
C state
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