LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 345
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
- LPC1767FBD100551 PDF datasheet #2
- LPC1767FBD100551 PDF datasheet #3
- LPC1769FBD100551 PDF datasheet #4
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- Download datasheet (6Mb)
NXP Semiconductors
UM10360
User manual
Fig 53. CAN controller block diagram
ACCEPTANCE
16.5.1 APB Interface Block (AIB)
16.5.2 Interface Management Logic (IML)
16.5.3 Transmit Buffers (TXB)
REGISTER
COMMON
APB BUS
STATUS
FILTER
NVIC
The APB Interface Block provides access to all CAN Controller registers.
The Interface Management Logic interprets commands from the CPU, controls internal
addressing of the CAN Registers and provides interrupts and status information to the
CPU.
The TXB represents a Triple Transmit Buffer, which is the interface between the Interface
Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is
able to store a complete message which can be transmitted over the CAN network. This
buffer is written by the CPU and read out by the BSP.
•
•
•
Nested Vectored Interrupt Controller (NVIC)
CAN Transceiver
Common Status Registers
MANAGEMENT
BUFFERS 1,2
BUFFERS 1
INTERFACE
TRANSMIT
RECEIVE
LOGIC
AND 3
AND 2
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
MANAGEMENT
PROCESSOR
CAN CORE
STREAM
ERROR
BLOCK
TIMING
LOGIC
LOGIC
BIT
BIT
TX
RX
Chapter 16: LPC17xx CAN1/2
TRANSCEIVER
CAN
UM10360
© NXP B.V. 2010. All rights reserved.
345 of 840
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