LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 36

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
Fig 9.
PLL0 block diagram
4.5.2 PLL0 register description
4.5.3 PLL0 Control register (PLL0CON - 0x400F C080)
pllclkin
PLLC
PLLE
PLL0 is controlled by the registers shown in
Warning: Improper setting of PLL0 values may result in incorrect operation of the
device!
Table 18.
[1]
The PLL0CON register contains the bits that enable and connect PLL0. Enabling PLL0
allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting PLL0 causes the processor and most chip functions to run from the PLL0
Name
PLL0CON
PLL0CFG
PLL0STAT
PLL0FEED PLL0 Feed Register. This register enables
NSEL
MSEL
[14:0]
[7:0]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
pd
PLL0 registers
N-DIVIDER
Description
PLL0 Control Register. Holding register for
updating PLL0 control bits. Values written to this
register do not take effect until a valid PLL0 feed
sequence has taken place.
PLL0 Configuration Register. Holding register for
updating PLL0 configuration values. Values
written to this register do not take effect until a
valid PLL0 feed sequence has taken place.
PLL0 Status Register. Read-back register for
PLL0 control and configuration information. If
PLL0CON or PLL0CFG have been written to, but
a PLL0 feed sequence has not yet occurred, they
will not reflect the current PLL0 state. Reading
this register provides the actual values controlling
the PLL0, as well as the PLL0 status.
loading of the PLL0 control and configuration
information from the PLL0CON and PLL0CFG
registers into the shadow registers that actually
affect PLL0 operation.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
refclk
M-DIVIDER
FREQUENCY
DETECTOR
PHASE-
Chapter 4: LPC17xx Clocking and power control
PLOCK
Table
FILTER
/2
18. More detailed descriptions follow.
CCO
Access Reset
R/W
R/W
RO
WO
value
0
0
0
NA
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
pllclk
Address
0x400F C080
0x400F C084
0x400F C088
0x400F C08C
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