LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 15
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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2.4 Memory re-mapping
2.5 AHB arbitration
2.6 Bus fault exceptions
UM10360
User manual
Table 5.
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the Cortex-M3. Refer to
Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset
feature.
Boot ROM re-mapping
Following a hardware reset, the Boot ROM is temporarily mapped to address 0. This is
normally transparent to the user. However, if execution is halted immediately after reset by
a debugger, it should correct the mapping for the user. See
The Multilayer AHB Matrix arbitrates between several masters. By default, the Cortex-M3
D-code bus has the highest priority, followed by the I-Code bus. All other masters share a
lower priority.
The LPC17xx generates Bus Fault exception if an access is attempted for an address that
is in a reserved or unassigned address region. The regions are areas of the memory map
that are not implemented for a specific derivative. These include all spaces marked
“reserved” in
APB1 peripheral
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 to 30
31
APB1 peripherals and base addresses
Figure
All information provided in this document is subject to legal disclaimers.
Base address
0x4008 0000
0x4008 4000
0x4008 8000
0x4008 C000
0x4009 0000
0x4009 4000
0x4009 8000
0x4009 C000
0x400A 0000
0x400A 4000
0x400A 8000
0x400A C000
0x400B 0000
0x400B 4000
0x400B 8000
0x400B C000
0x400C 0000 to 0x400F 8000
0x400F C000
3.
Rev. 2 — 19 August 2010
Section 6.4
Peripheral name
reserved
reserved
SSP0
DAC
Timer 2
Timer 3
UART2
UART3
I
reserved
I
reserved
Repetitive interrupt timer
reserved
Motor control PWM
Quadrature Encoder Interface
reserved
System control
2
2
Chapter 2: LPC17xx Memory map
C2
S
and
Section
Section 34.4.3.5
33.6.
UM10360
© NXP B.V. 2010. All rights reserved.
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