LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 323

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description
Table 295: UART1 Interrupt Identification Register (U1IIR - address 0x4001 0008) bit description
UM10360
User manual
Bit
8
9
31:10 -
Bit
0
3:1
5:4
7:6
8
9
31:10 -
Symbol
ABEOIntEn
ABTOIntEn
Symbol
IntStatus
IntId
-
FIFO Enable
ABEOInt
ABTOInt
15.4.5 UART1 Interrupt Identification Register (U1IIR - 0x4001 0008)
Value Description
Value Description
0
011
0
1
0
1
010
110
001
000
1
The U1IIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during
an U1IIR access, the interrupt is recorded for the next U1IIR access.
Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in
Enables the end of auto-baud interrupt.
Disable end of auto-baud Interrupt.
Enable end of auto-baud Interrupt.
Enables the auto-baud time-out interrupt.
Disable auto-baud time-out Interrupt.
Enable auto-baud time-out Interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Interrupt status. Note that U1IIR[0] is active low. The pending interrupt can be
determined by evaluating U1IIR[3:1].
At least one interrupt is pending.
No interrupt is pending.
Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the
UART1 Rx or TX FIFO. All other combinations of U1IER[3:1] not listed below
are reserved (100,101,111).
1 - Receive Line Status (RLS).
2a - Receive Data Available (RDA).
2b - Character Time-out Indicator (CTI).
3 - THRE Interrupt.
4 - Modem Interrupt.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Copies of U1FCR[0].
End of auto-baud interrupt. True if auto-baud has finished successfully and
interrupt is enabled.
Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is
enabled.
Reserved, the value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table
296. Given the status of U1IIR[3:0], an
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
NA
Reset
Value
1
0
NA
0
0
0
323 of 840
Reset
Value
0
0
NA