LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 439

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
19.8 Register description
Table 383. I
UM10360
User manual
Generic
Name
I2CONSET I2C Control Set Register. When a one is written to
I2STAT
I2DAT
I2ADR0
I2SCLH
I2SCLL
I2CONCLR I2C Control Clear Register. When a one is written
MMCTRL
I2ADR1
2
C register map
Description
a bit of this register, the corresponding bit in the I
control register is set. Writing a zero has no effect on
the corresponding bit in the I
I2C Status Register. During I
register provides detailed status codes that allow
software to determine the next action needed.
I2C Data Register. During master or slave transmit
mode, data to be transmitted is written to this
register. During master or slave receive mode, data
that has been received may be read from this
register.
I2C Slave Address Register 0. Contains the 7-bit
slave address for operation of the I
slave mode, and is not used in master mode. The
least significant bit determines whether a slave
responds to the General Call address.
SCH Duty Cycle Register High Half Word.
Determines the high time of the I
SCL Duty Cycle Register Low Half Word.
Determines the low time of the I
and I2nSCLH together determine the clock
frequency generated by an I
times used in slave mode.
to a bit of this register, the corresponding bit in the
I
effect on the corresponding bit in the I
register.
Monitor mode control register.
I2C Slave Address Register 1. Contains the 7-bit
slave address for operation of the I
slave mode, and is not used in master mode. The
least significant bit determines whether a slave
responds to the General Call address.
2
C control register is cleared. Writing a zero has no
Each I
Remark: In the LPC17xx, the following registers have been added to support response to
multiple addresses in Slave mode and a new Monitor mode: I2ADR1 to 3, I2MASK0 To 3,
MMCTRL, and I2DATA_BUFFER.
2
C interface contains 16 registers as shown in
2
2
All information provided in this document is subject to legal disclaimers.
C master and certain
C control register.
2
C operation, this
2
2
C clock. I2nSCLL
C clock.
2
2
C interface in
C interface in
Rev. 2 — 19 August 2010
2
C control
2
C
Access Reset
R/W
RO
R/W
R/W
R/W
R/W
WO
R/W
R/W
value
0x00
0xF8
0x00
0x00
0x04
0x04
NA
0x00
0x00
[1]
Table 383
I
I2C0CONSET - 0x4001 C000
I2C1CONSET - 0x4005 C000
I2C2CONSET - 0x400A 0000
I2C0STAT - 0x4001 C004
I2C1STAT - 0x4005 C004
I2C2STAT - 0x400A 0004
I2C0DAT - 0x4001 C008
I2C1DAT - 0x4005 C008
I2C2DAT - 0x400A 0008
I2C0ADR0 - 0x4001 C00C
I2C1ADR0 - 0x4005 C00C
I2C2ADR0 - 0x400A 000C
I2C0SCLH - 0x4001 C010
I2C1SCLH - 0x4005 C010
I2C2SCLH - 0x400A 0010
I2C0SCLL - 0x4001 C014
I2C1SCLL - 0x4005 C014
I2C2SCLL - 0x400A 0014
I2C0CONCLR - 0x4001 C018
I2C1CONCLR - 0x4005 C018
I2C2CONCLR - 0x400A 0018
I2C0MMCTRL - 0x4001 C01C
I2C1MMCTRL - 0x4005 C01C
I2C2MMCTRL - 0x400A 001C
I2C0ADR1 - 0x4001 C020
I2C1ADR1 - 0x4005 C020
I2C2ADR1 - 0x400A 0020
2
Cn Name & Address
Chapter 19: LPC17xx I2C0/1/2
below.
UM10360
© NXP B.V. 2010. All rights reserved.
439 of 840