LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 298

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

14.1 Basic configuration
14.2 Features
UM10360
User manual
The UART0/2/3 peripherals are configured using the following registers:
1. Power: In the PCONP register
2. Peripheral clock: In the PCLKSEL0 register
3. Baud rate: In register U0/2/3LCR
4. UART FIFO: Use bit FIFO enable (bit 0) in register U0/2/3FCR
5. Pins: Select UART pins through the PINSEL registers and pin modes through the
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U0/2/3LCR
7. DMA: UART0/2/3 transmit and receive functions can operate with the GPDMA
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UM10360
Chapter 14: LPC17xx UART0/2/3
Rev. 2 — 19 August 2010
Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled
(PCUART2/3 = 0).
PCLKSEL1 register
to registers DLL
needed, set the fractional baud rate in the fractional divider register
FIFO.
PINMODE registers
Remark: UART receive pins should not have pull-down resistors enabled.
(Table
the NVIC using the appropriate Interrupt Set Enable register.
controller (see
Data sizes of 5, 6, 7, and 8 bits.
Parity generation and checking: odd, even mark, space or none.
One or two stop bits.
16 byte Receive and Transmit FIFOs.
Built-in baud rate generator, including a fractional rate divider for great versatility.
Supports DMA for both transmit and receive.
Auto-baud capability
Break generation and detection.
Multiprocessor addressing mode.
IrDA mode to support infrared communication.
Support for software flow control.
279). This enables access to U0/2/3IER
All information provided in this document is subject to legal disclaimers.
Table
(Table
Rev. 2 — 19 August 2010
(Table
(Section
543).
273) and DLM
41), select PCLK_UART2/3.
8.5).
(Table
(Table
46), set bits PCUART0/2/3.
(Table
279), set bit DLAB =1. This enables access
(Table
274) for setting the baud rate. Also, if
(Table
40), select PCLK_UART0; in the
275). Interrupts are enabled in
(Table
© NXP B.V. 2010. All rights reserved.
(Table
278) to enable
User manual
285).
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