LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 833

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers
27.1
27.2
27.3
27.4
27.5
27.6
27.6.1
27.6.2
27.6.2.1
27.6.2.2
27.6.2.3
27.6.2.4
27.6.2.5
27.6.2.6
27.6.3
Chapter 28: LPC17xx Watchdog Timer (WDT)
28.1
28.2
28.3
28.4
28.4.1
28.4.2
Chapter 29: LPC17xx Analog-to-Digital Converter (ADC)
29.1
29.2
29.3
29.4
29.5
29.5.1
29.5.2
Chapter 30: LPC17xx Digital-to-Analog Converter (DAC)
30.1
UM10360
User manual
Basic configuration . . . . . . . . . . . . . . . . . . . . 558
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 560
Register description . . . . . . . . . . . . . . . . . . . 560
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Register description . . . . . . . . . . . . . . . . . . . 570
Basic configuration . . . . . . . . . . . . . . . . . . . . 574
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 575
Register description . . . . . . . . . . . . . . . . . . . 576
Basic configuration . . . . . . . . . . . . . . . . . . . . 582
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . 562
Miscellaneous register group . . . . . . . . . . . . 562
Interrupt Location Register (ILR - 0x4002
4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Clock Control Register (CCR - 0x4002 4008) 562
Counter Increment Interrupt Register (CIIR -
0x4002 400C) . . . . . . . . . . . . . . . . . . . . . . . . 563
Alarm Mask Register (AMR - 0x4002 4010) . 563
RTC Auxiliary control register (RTC_AUX -
0x4002 405C) . . . . . . . . . . . . . . . . . . . . . . . . 564
RTC Auxiliary Enable register (RTC_AUXEN -
0x4002 4058) . . . . . . . . . . . . . . . . . . . . . . . . 564
Consolidated time registers . . . . . . . . . . . . . 565
Watchdog Mode register (WDMOD -
0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 571
Watchdog Timer Constant register (WDTC -
0x4000 0004) . . . . . . . . . . . . . . . . . . . . . . . . 572
A/D Control Register (AD0CR - 0x4003
4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
A/D Global Data Register (AD0GDR -
0x4003 4004) . . . . . . . . . . . . . . . . . . . . . . . . 578
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
27.6.3.1
27.6.3.2
27.6.3.3
27.6.4
27.6.4.1
27.6.4.2
27.6.5
27.6.6
27.6.6.1
27.6.7
27.7
28.4.3
28.4.4
28.4.5
28.5
29.5.3
29.5.4
29.5.5
29.5.6
29.6
29.6.1
29.6.2
29.6.3
29.6.4
30.2
RTC usage notes. . . . . . . . . . . . . . . . . . . . . . 568
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 573
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Consolidated Time Register 0 (CTIME0 -
0x4002 4014) . . . . . . . . . . . . . . . . . . . . . . . . 565
Consolidated Time Register 1 (CTIME1 -
0x4002 4018) . . . . . . . . . . . . . . . . . . . . . . . . 565
Consolidated Time Register 2 (CTIME2 -
0x4002 401C) . . . . . . . . . . . . . . . . . . . . . . . 565
Time Counter Group . . . . . . . . . . . . . . . . . . 566
Leap year calculation . . . . . . . . . . . . . . . . . . 566
Calibration register (CALIBRATION - address
0x4002 4040) . . . . . . . . . . . . . . . . . . . . . . . . 566
Calibration procedure. . . . . . . . . . . . . . . . . . 567
Backward calibration . . . . . . . . . . . . . . . . . . . 567
Forward calibration . . . . . . . . . . . . . . . . . . . . 567
General purpose registers . . . . . . . . . . . . . 568
General purpose registers 0 to 4 (GPREG0 to
GPREG4 - addresses 0x4002 4044 to 0x4002
4054) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Alarm register group . . . . . . . . . . . . . . . . . . 568
Watchdog Feed register (WDFEED -
0x4000 0008) . . . . . . . . . . . . . . . . . . . . . . . . 572
Watchdog Timer Value register (WDTV -
0x4000 000C) . . . . . . . . . . . . . . . . . . . . . . . 572
Watchdog Timer Clock Source Selection register
(WDCLKSEL - 0x4000 0010). . . . . . . . . . . . 572
A/D Interrupt Enable register (AD0INTEN -
0x4003 400C) . . . . . . . . . . . . . . . . . . . . . . . 578
A/D Data Registers (AD0DR0 to AD0DR7 -
0x4003 4010 to 0x4003 402C). . . . . . . . . . . 579
A/D Status register (ADSTAT - 0x4003 4030) 580
A/D Trim register (ADTRIM - 0x4003 4034). 580
Hardware-triggered conversion . . . . . . . . . . 581
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
Accuracy vs. digital receiver . . . . . . . . . . . . 581
DMA control . . . . . . . . . . . . . . . . . . . . . . . . . 581
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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