LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 392
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
- LPC1767FBD100551 PDF datasheet #2
- LPC1767FBD100551 PDF datasheet #3
- LPC1769FBD100551 PDF datasheet #4
- Current page: 392 of 840
- Download datasheet (6Mb)
NXP Semiconductors
UM10360
User manual
Fig 69. Message overwritten indicated by message lost
semaphore
MsgLostx
IntPndx
look-up
access
table
bits
16.16.3.6 Scenario 4: Clearing Message Lost bit
SEM
write
01
ID,
This scenario is a special case in which the lost message bit of an object gets set during
an overwrite of a none read message object (2
of that object by Software (1
write clears the Message Lost bit. Every “write ID, SEM” clears Message Lost bit if no
pending Interrupt of that object is set.
1st Object
write
D1
write
write
D2
write
SEM
11
SEM
read
All information provided in this document is subject to legal disclaimers.
write
SEM
01
ID,
Rev. 2 — 19 August 2010
write
2nd Object
D1
write
st
write
D2
Object read) clears the pending Interrupt. The 3
Interrupt Service
write
SEM
1st Object
11
Routine
read
clear
SEM
00
nd
Object write). The subsequent read out
read
D1
read
D2
SEM
Chapter 16: LPC17xx CAN1/2
read
SEM
write
ID,
01
message
handler
access
write
UM10360
3rd Object
D1
© NXP B.V. 2010. All rights reserved.
write
write
D2
processor
access
write
SEM
ARM
rd
11
Object
392 of 840
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