LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 733

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.3.1.3.6 Exception mask registers
Interruptible-continuable instructions:
of an LDM or STM instruction, the processor:
After servicing the interrupt, the processor:
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
If-Then block:
instruction. Each instruction in the block is conditional. The conditions for the instructions
are either all the same, or some can be the inverse of others. See
more information.
The exception mask registers disable the handling of exceptions by the processor.
Disable exceptions where they might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS
instruction to change the value of PRIMASK or FAULTMASK. See
“MRS”,
Priority Mask Register:
configurable priority. See the register summary in
assignments are shown in
Table 631.
Fault Mask Register:
except for Non-Maskable Interrupt (NMI). See the register summary in
attributes. The bit assignments are shown in
Table 632.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except
the NMI handler.
Base Priority Mask Register:
exception processing. When BASEPRI is set to a nonzero value, it prevents the activation
of all exceptions with same or lower priority level as the BASEPRI value. See the register
summary in
Bits
[31:1]
[0]
Bits
[31:1]
[0]
•
•
•
•
stops the load multiple or store multiple instruction operation temporarily.
stores the next register operand in the multiple operation to EPSR bits[15:12].
returns to the register pointed to by bits[15:12].
resumes execution of the multiple load or store instruction.
Section 34.2.10.7
Name
-
PRIMASK
Name
-
FAULTMASK
PRIMASK register bit assignments
FAULTMASK register bit assignments
Table 626
The If-Then block contains up to four instructions following a 16-bit IT
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
The FAULTMASK register prevents activation of all exceptions
for its attributes. The bit assignments are shown in
Function
Reserved
0 = no effect
1 = prevents the activation of all exceptions except for NMI.
The PRIMASK register prevents activation of all exceptions with
“MSR”, and
Table
Function
Reserved
0 = no effect
1 = prevents the activation of all exceptions with configurable priority.
The BASEPRI register defines the minimum priority for
631.
Section 34.2.10.2 “CPS”
Chapter 34: Appendix: Cortex-M3 user guide
When an interrupt occurs during the execution
Table
Table 626
632.
for its attributes. The bit
for more information.
Section 34.2.9.3 “IT”
Section 34.2.10.6
UM10360
© NXP B.V. 2010. All rights reserved.
Table 626
Table
633.
733 of 840
for its
for