LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 527

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 455. MCPWM Control read address (MCCON - 0x400B 8000) bit description
Table 456. MCPWM Control set address (MCCON_SET - 0x400B 8004) bit description
UM10360
User manual
Bit
15:13
16
17
18
19
20
28:21
29
30
31
Bit
31:0
Description
Writing ones to this address sets the corresponding bits in the MCCON register. See
Symbol
-
RUN2
CENTER2
POLA2
DTE2
DISUP2
-
INVBDC
ACMODE
DCMODE
25.7.1.2 MCPWM Control set address (MCCON_SET - 0x400B 8004)
Value Description
-
0
1
0
1
0
1
0
1
0
1
-
0
1
0
1
0
1
Writing ones to this write-only address sets the corresponding bits in MCCON.
Reserved.
Stops/starts timer channel 2.
Stop.
Run.
Edge/center aligned operation for channel 2.
Edge-aligned.
Center-aligned.
Selects polarity of the MCOA2 and MCOB2 pins.
Passive state is LOW, active state is HIGH.
Passive state is HIGH, active state is LOW.
Controls the dead-time feature for channel 1.
Dead-time disabled.
Dead-time enabled.
Enable/disable updates of functional registers for channel 2 (see
Section
Functional registers are updated from the write registers at the end of each PWM
cycle.
Functional registers remain the same as long as the timer is running.
Reserved.
Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set
to 1 only in 3-phase DC mode.
The MCOB outputs have opposite polarity from the MCOA outputs (aside from
dead time).
The MCOB outputs have the same basic polarity as the MCOA outputs. (see
Section
3-phase AC mode select (see
3-phase AC-mode off: Each PWM channel uses its own timer-counter and period
register.
3-phase AC-mode on: All PWM channels use the timer-counter and period register
of channel 0.
3-phase DC mode select (see
3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)
3-phase DC mode on: The internal MCOA0 output is routed through the MCCP (i.e.
a mask) register to all six PWM outputs.
25.7.6.1).
25.8.6)
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section
Section
25.8.7).
25.8.6).
Chapter 25: LPC17xx Motor control PWM
Table
Section
455.
UM10360
© NXP B.V. 2010. All rights reserved.
25.8.2,
527 of 840
Reset
value
0
0
0
0
0
0
0
0