LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 832

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
25.7.6
25.7.6.1
25.7.7
25.7.7.1
25.7.7.2
25.7.7.3
25.7.8
25.7.9
25.7.10
25.7.10.1 MCPWM Capture read addresses (MCCAP0-2 -
Chapter 26: LPC17xx Quadrature Encoder Interface (QEI)
26.1
26.2
26.3
26.4
26.4.1
26.4.1.1
26.4.1.2
26.4.2
26.4.3
26.4.4
26.5
26.6
26.6.1
26.6.2
26.6.2.1
26.6.2.2
26.6.2.3
26.6.3
26.6.3.1
26.6.3.2
26.6.3.3
26.6.3.4
26.6.3.5
UM10360
User manual
Basic configuration . . . . . . . . . . . . . . . . . . . . 543
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Functional description . . . . . . . . . . . . . . . . . 545
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 548
Register description . . . . . . . . . . . . . . . . . . . 549
MCPWM Limit 0-2 registers (MCLIM0-2 -
0x400B 8024, 0x400B 8028, 0x400B 802C) 533
Match and Limit write and operating registers 533
MCPWM Match 0-2 registers (MCMAT0-2 -
0x400B 8030, 0x400B 8034, 0x400B 8038) . 534
Match register in Edge-Aligned mode. . . . . . 534
Match register in Center-Aligned mode . . . . 534
0 and 100% duty cycle . . . . . . . . . . . . . . . . . 534
MCPWM Dead-time register (MCDT -
0x400B 803C). . . . . . . . . . . . . . . . . . . . . . . . 535
MCPWM Commutation Pattern register (MCCP -
0x400B 8040) . . . . . . . . . . . . . . . . . . . . . . . . 535
MCPWM Capture Registers . . . . . . . . . . . . . 536
0x400B 8044, 0x400B 8048, 0x400B 804C) 536
Input signals . . . . . . . . . . . . . . . . . . . . . . . . . 545
Quadrature input signals . . . . . . . . . . . . . . . 545
Digital input filtering . . . . . . . . . . . . . . . . . . . 546
Position capture . . . . . . . . . . . . . . . . . . . . . . 546
Velocity capture . . . . . . . . . . . . . . . . . . . . . . 546
Velocity compare . . . . . . . . . . . . . . . . . . . . . 547
Register summary . . . . . . . . . . . . . . . . . . . . 549
Control registers . . . . . . . . . . . . . . . . . . . . . . 550
QEI Control register (QEICON - 0x400B
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
QEI Configuration register (QEICONF - 0x400B
C008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
QEI Status register (QEISTAT - 0x400B
C004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Position, index and timer registers . . . . . . . . 551
QEI Position register (QEIPOS - 0x400B
C00C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
QEI Maximum Position register (QEIMAXPOS -
0x400B C010). . . . . . . . . . . . . . . . . . . . . . . . 551
QEI Position Compare register 0 (CMPOS0 -
0x400B C014). . . . . . . . . . . . . . . . . . . . . . . . 551
QEI Position Compare register 1 (CMPOS1 -
0x400B C018). . . . . . . . . . . . . . . . . . . . . . . . 551
QEI Position Compare register 2 (CMPOS2 -
0x400B C01C) . . . . . . . . . . . . . . . . . . . . . . . 552
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
25.7.10.2 MCPWM Capture clear address (MCCAP_CLR -
25.8
25.8.1
25.8.2
25.8.3
25.8.4
25.8.5
25.8.6
25.8.7
25.8.8
26.6.3.6
26.6.3.7
26.6.3.8
26.6.3.9
26.6.3.10 QEI Velocity register (QEIVEL - 0x400B
26.6.3.11 QEI Velocity Capture register (QEICAP - 0x400B
26.6.3.12 QEI Velocity Compare register (VELCOMP -
26.6.3.13 QEI Digital Filter register (FILTER - 0x400B
26.6.4
26.6.4.1
26.6.4.2
26.6.4.3
26.6.4.4
26.6.4.5
26.6.4.6
PWM operation . . . . . . . . . . . . . . . . . . . . . . . 537
0x400B 8074). . . . . . . . . . . . . . . . . . . . . . . . 536
Pulse-width modulation . . . . . . . . . . . . . . . . 537
Edge-aligned PWM without dead-time. . . . . . 537
Center-aligned PWM without dead-time . . . . 537
Dead-time counter . . . . . . . . . . . . . . . . . . . . . 538
Shadow registers and simultaneous updates 539
Fast Abort (ABORT). . . . . . . . . . . . . . . . . . . 539
Capture events. . . . . . . . . . . . . . . . . . . . . . . 539
External event counting (Counter mode) . . . 540
Three-phase DC mode . . . . . . . . . . . . . . . . 540
Three phase AC mode. . . . . . . . . . . . . . . . . 541
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
QEI Index Count register (INXCNT - 0x400B
C020) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
QEI Index Compare register (INXCMP - 0x400B
C024) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
QEI Timer Reload register (QEILOAD - 0x400B
C028) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
QEI Timer register (QEITIME - 0x400B
C02C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
C030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
C034) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
0x400B C038) . . . . . . . . . . . . . . . . . . . . . . . 553
C03C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Interrupt registers. . . . . . . . . . . . . . . . . . . . . 554
QEI Interrupt Status register (QEIINTSTAT)
QEI Interrupt Set register (QEISET - 0x400B
CFEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
QEI Interrupt Clear register (QEICLR - 0x400B
CFE8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
QEI Interrupt Enable register (QEIIE - 0x400B
CFE4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
QEI Interrupt Enable Set register (QEIIES -
0x400B CFDC). . . . . . . . . . . . . . . . . . . . . . . 556
QEI Interrupt Enable Clear register (QEIIEC -
0x400B CFD8) . . . . . . . . . . . . . . . . . . . . . . . 557
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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