LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 478

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 408: Receive FIFO register (I2RXFIFO - address 0x400A 800C) bit description
Table 409: Status Feedback register (I2SSTATE - address 0x400A 8010) bit description
Table 410: DMA Configuration register 1 (I2SDMA1 - address 0x400A 8014) bit description
UM10360
User manual
Bit
31:0 I2SRXFIFO
Bit
0
1
2
7:3
11:8
15:12
19:16
31:20
Bit
0
1
7:2
11:8
15:12
19:16
31:20
Symbol
Symbol
irq
dmareq1
dmareq2
Unused
rx_level
-
tx_level
-
Symbol
rx_dma1_enable
tx_dma1_enable
-
rx_depth_dma1
-
tx_depth_dma1
-
20.5.5 Status Feedback register (I2SSTATE - 0x400A 8010)
20.5.6 DMA Configuration Register 1 (I2SDMA1 - 0x400A 8014)
Description
This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by
comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the I2SIRQ
register.
This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by
comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the
I2SDMA1 register.
This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by
comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the
I2SDMA2 register.
Unused.
Reflects the current level of the Receive FIFO.
Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
Reflects the current level of the Transmit FIFO.
Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
Description
8
×
The I2SSTATE register provides status information about the I
of bits in I2SSTATE are shown in
The I2SDMA1 register controls the operation of DMA request 1. The function of bits in
I2SDMA1 are shown in
for details of DMA operation.
32-bit transmit FIFO.
Description
When 1, enables DMA1 for I
When 1, enables DMA1 for I
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Set the FIFO level that triggers a receive DMA request on DMA1.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Set the FIFO level that triggers a transmit DMA request on DMA1.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table
410. Refer to the General Purpose DMA Controller chapter
2
2
S receive.
S transmit.
Table
409.
2
Chapter 20: LPC17xx I2S
S interface. The meaning
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
level = 0
478 of 840
Reset
Value
1
1
1
0
0
NA
0
NA
Reset
Value
0
0
0
0
NA
0
NA