LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 63

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
Some peripherals, particularly those that include analog functions, may consume power
that is not clock dependent. These peripherals may contain a separate disable control that
turns off additional circuitry to reduce power. Information on peripheral specific power
saving features may be found in the chapter describing that peripheral.
Each bit in PCONP controls one peripheral as shown in
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that
peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the
I
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
Table 46.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
2
C1 interface is enabled. If bit 19 is 0, the I
Symbol
-
PCTIM0
PCTIM1
PCUART0
PCUART1
-
PCPWM1
PCI2C0
PCSPI
PCRTC
PCSSP1
-
PCADC
PCCAN1
PCCAN2
PCGPIO
PCRIT
PCMCPWM Motor Control PWM
PCQEI
PCI2C1
-
PCSSP0
PCTIM2
PCTIM3
PCUART2
PCUART3
PCI2C2
Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit
description
All information provided in this document is subject to legal disclaimers.
Description
Reserved.
Timer/Counter 0 power/clock control bit.
Timer/Counter 1 power/clock control bit.
UART0 power/clock control bit.
UART1 power/clock control bit.
Reserved.
PWM1 power/clock control bit.
The I
The SPI interface power/clock control bit.
The RTC power/clock control bit.
The SSP 1 interface power/clock control bit.
Reserved.
A/D converter (ADC) power/clock control bit.
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
CAN Controller 1 power/clock control bit.
CAN Controller 2 power/clock control bit.
Power/clock control bit for IOCON, GPIO, and GPIO interrupts.
Repetitive Interrupt Timer power/clock control bit.
Quadrature Encoder Interface power/clock control bit.
The I
Reserved.
The SSP0 interface power/clock control bit.
Timer 2 power/clock control bit.
Timer 3 power/clock control bit.
UART 2 power/clock control bit.
UART 3 power/clock control bit.
I
2
C interface 2 power/clock control bit.
Rev. 2 — 19 August 2010
2
2
C0 interface power/clock control bit.
C1 interface power/clock control bit.
Chapter 4: LPC17xx Clocking and power control
2
C1 interface is disabled.
Table
46.
UM10360
© NXP B.V. 2010. All rights reserved.
63 of 840
Reset
value
NA
1
1
1
1
NA
1
1
1
1
1
NA
0
0
0
1
0
0
0
1
NA
1
0
0
0
0
1