LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 42
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
- LPC1767FBD100551 PDF datasheet #2
- LPC1767FBD100551 PDF datasheet #3
- LPC1769FBD100551 PDF datasheet #4
- Current page: 42 of 840
- Download datasheet (6Mb)
NXP Semiconductors
UM10360
User manual
4.5.11 Procedure for determining PLL0 settings
Table 26.
PLL0 parameter determination can be simplified by using a spreadsheet available from
NXP. To determine PLL0 parameters by hand, the following general procedure may be
used:
In general, it is better to use a smaller value for N, to reduce the level of multiplication that
must be accomplished by the CCO. Due to the difficulty in finding the best values in some
cases, it is recommended to use a spreadsheet or similar method to show many
possibilities at once, from which an overall best choice may be selected. A spreadsheet is
available from NXP for this purpose.
1. Determine if the application requires use of the USB interface, and whether it will be
2. Choose the desired processor operating frequency (CCLK). This may be based on
3. Choose a value for the PLL input frequency (F
4. Calculate values for M and N to produce a sufficiently accurate F
clocked from PLL0. The USB requires a 50% duty cycle clock of 48 MHz within a very
small tolerance, which means that F
(i.e. an integer multiple of 96 MHz), within a very small tolerance.
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
frequency than that of the processor (see
Section 4.8 “Power control” on page
multiple of the desired CCLK frequency, bearing in mind the requirement for USB
support in [1] above, and that lower values of F
the main oscillator, the RTC oscillator, or the on-chip RC oscillator. For USB support,
the main oscillator should be used. Bear in mind that if PLL1 rather than PLL0 is used
to clock the USB subsystem, this affects the choice of the main oscillator frequency.
desired M value -1 will be written to the MSEL0 field in PLL0CFG. The desired N value
-1 will be written to the NSEL0 field in PLL0CFG.
12085
13733
15381
16479
19775
21973
4272
5127
6042
6750
7324
8057
9613
Additional Multiplier Values for use with a Low Frequency Clock Input
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
10254
12207
13916
15564
17578
20508
23071
4395
5188
6075
6836
7425
8100
Low Frequency PLL Multipliers
Chapter 4: LPC17xx Clocking and power control
CCO
58). Find a value for F
10376
12817
14099
15625
18127
20599
23438
8545
4578
5400
6104
6866
7690
must be an even integer multiple of 48 MHz
Section 4.7 “Clock dividers” on page 54
IN
CCO
). This can be a clock obtained from
result in lower power dissipation.
10986
13184
14420
15869
20874
23804
18311
4725
5493
6409
6958
7813
8789
CCO
that is close to a
CCO
UM10360
© NXP B.V. 2010. All rights reserved.
frequency. The
13672
14648
19226
24170
11719
16113
21149
4807
5859
6592
7050
7935
9155
42 of 840
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