LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 602

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 562. DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)
UM10360
User manual
Bit
1:0
31:2
31.5.20.1 Protection and access information
Name
-
LLI
31.5.20 DMA channel control registers (DMACCxControl - 0x5000 41xC)
The eight read/write DMACCxControl Registers (DMACC0Control to DMACC7Control)
contain DMA channel control information such as the transfer size, burst size, and transfer
width. Each register is programmed directly by software before the DMA channel is
enabled. When the channel is enabled the register is updated by following the linked list
when a complete packet of data has been transferred. Reading the register while the
channel is active does not give useful information. This is because by the time software
has processed the value read, the channel may have advanced. It is intended to be
read-only when a channel has stopped.
DMACCxControl Register.
AHB access information is provided to the source and/or destination peripherals when a
transfer occurs, although on the LPC17xx this has no effect. The transfer information is
provided by programming the DMA channel (the Prot bits of the DMACCxControl
Register, and the Lock bit of the DMACCxConfig Register). These bits are programmed
by software, and can be used by peripherals. Three bits of information are provided, and
are used as shown in
Function
Reserved, and must be written as 0.
Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 2 — 19 August 2010
563.
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Table 563
shows the bit assignments of the
UM10360
© NXP B.V. 2010. All rights reserved.
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