LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 761

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
[1]
UM10360
User manual
Each array element corresponds to a single NVIC register, for example the element
34.4.2.2 Interrupt Set-enable Registers
34.4.2.3 Interrupt Clear-enable Registers
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority
Registers. For more information see the description of the NVIC_SetPriority function in
Section 34.4.2.10.1 “NVIC programming
IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that
have one bit per interrupt.
Table 645. Mapping of interrupts to the interrupt variables
The ISER0-ISER3 registers enable interrupts, and show which interrupts are enabled.
See:
The bit assignments are shown in
Table 646. ISER bit assignments
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to
pending, but the NVIC never activates the interrupt, regardless of its priority.
The ICER0-ICER3 registers disable interrupts, and show which interrupts are enabled.
See:
The bit assignments are shown in
Interrupts
0-31
32-63
64-95
96-127
Bits
[31:0]
•
•
•
•
the register summary in
Table 645
the register summary in
Table 645
CMSIS array elements
Set-enable
ISER[0]
ISER[1]
ISER[2]
ISER[3]
for which interrupts are controlled by each register.
for which interrupts are controlled by each register.
Name
SETENA
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Clear-enable
ICER[0]
ICER[1]
ICER[2]
ICER[3]
Table 644
Table 644
Function
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Table
Table
[1]
for the register attributes
for the register attributes
646.
647.
hints”.
Chapter 34: Appendix: Cortex-M3 user guide
Set-pending
ISPR[0]
ISPR[1]
ISPR[2]
ISPR[3]
Table 645
ICER[1]
corresponds to the ICER1 register.
shows how the interrupts, or
Clear-pending
ICPR[0]
ICPR[1]
ICPR[2]
ICPR[3]
UM10360
© NXP B.V. 2010. All rights reserved.
Active Bit
IABR[0]
IABR[1]
IABR[2]
IABR[3]
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