LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 836
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
33.7
Chapter 34: Appendix: Cortex-M3 user guide
34.1
34.1.1
34.1.1.1
34.1.1.2
34.1.1.3
34.1.1.4
34.2
34.2.1
34.2.2
34.2.3
34.2.3.1
34.2.3.2
34.2.3.3
34.2.3.3.1 Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
34.2.3.3.2 Register with optional shift . . . . . . . . . . . . . . 652
34.2.3.4
34.2.3.4.1 ASR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
34.2.3.4.2 LSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
34.2.3.4.3 LSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
34.2.3.4.4 ROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
34.2.3.4.5 RRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
34.2.3.5
34.2.3.6
34.2.3.7
34.2.3.7.1 The condition flags . . . . . . . . . . . . . . . . . . . . 657
34.2.3.7.2 Condition code suffixes . . . . . . . . . . . . . . . . 657
34.2.3.8
34.2.3.8.1 Example: Instruction width selection . . . . . . 659
34.2.4
34.2.4.1
34.2.4.1.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
34.2.4.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
34.2.4.1.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 661
34.2.4.1.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 661
34.2.4.1.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
34.2.4.2
34.2.4.2.1 Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
34.2.4.2.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
34.2.4.2.3 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . 663
34.2.4.2.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 663
UM10360
User manual
JTAG TAP Identification . . . . . . . . . . . . . . . . 643
ARM Cortex-M3 User Guide: Introduction. . 644
ARM Cortex-M3 User Guide: Instruction Set 647
About the processor and core peripherals . . 644
System level interface . . . . . . . . . . . . . . . . . 645
Integrated configurable debug . . . . . . . . . . . 645
Cortex-M3 processor features and benefits
summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
Cortex-M3 core peripherals . . . . . . . . . . . . . 646
Instruction set summary . . . . . . . . . . . . . . . . 647
Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647
Intrinsic functions . . . . . . . . . . . . . . . . . . . . . 650
About the instruction descriptions. . . . . . . . . 650
Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Restrictions when using PC or SP . . . . . . . . 651
Flexible second operand . . . . . . . . . . . . . . . 651
Shift Operations . . . . . . . . . . . . . . . . . . . . . . 652
Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .653
Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .653
Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .654
Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .654
Address alignment . . . . . . . . . . . . . . . . . . . . 655
PC-relative expressions . . . . . . . . . . . . . . . . 656
Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .656
Conditional execution . . . . . . . . . . . . . . . . . . 656
Instruction width selection. . . . . . . . . . . . . . . 658
Memory access instructions . . . . . . . . . . . . . 660
ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
LDR and STR, immediate offset . . . . . . . . . . 662
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
34.2.4.2.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 664
34.2.4.3
34.2.4.3.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
34.2.4.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
34.2.4.3.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 665
34.2.4.3.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 666
34.2.4.3.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
34.2.4.4
34.2.4.4.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
34.2.4.4.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
34.2.4.4.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 667
34.2.4.4.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 667
34.2.4.4.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
34.2.4.5
34.2.4.5.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
34.2.4.5.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
34.2.4.5.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 669
34.2.4.5.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 670
34.2.4.5.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
34.2.4.6
34.2.4.6.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
34.2.4.6.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
34.2.4.6.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 672
34.2.4.6.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 672
34.2.4.6.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
34.2.4.6.6 Incorrect examples . . . . . . . . . . . . . . . . . . . 672
34.2.4.7
34.2.4.7.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
34.2.4.7.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
34.2.4.7.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 673
34.2.4.7.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 673
34.2.4.7.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
34.2.4.8
34.2.4.8.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
34.2.4.8.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
34.2.4.8.3 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 674
34.2.4.8.4 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 675
34.2.4.8.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
34.2.4.9
34.2.4.9.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
34.2.4.9.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
34.2.4.9.3 Condition flags . . . . . . . . . . . . . . . . . . . . . . . 676
34.2.4.9.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
34.2.5
34.2.5.1
34.2.5.1.1 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
34.2.5.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
LDR and STR, register offset . . . . . . . . . . . . 665
LDR and STR, unprivileged . . . . . . . . . . . . . 667
LDR, PC-relative . . . . . . . . . . . . . . . . . . . . . 669
LDM and STM . . . . . . . . . . . . . . . . . . . . . . . 671
PUSH and POP . . . . . . . . . . . . . . . . . . . . . . 673
LDREX and STREX . . . . . . . . . . . . . . . . . . . 674
CLREX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
General data processing instructions. . . . . . 677
ADD, ADC, SUB, SBC, and RSB. . . . . . . . . 678
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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