LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 413

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
18.4 Pin descriptions
Table 368. SSP pin descriptions
18.5 Bus description
UM10360
User manual
Pin
Name
SCK0/1
SSEL0/1 I/O
MISO0/1 I/O
MOSI0/1 I/O
Type
I/O
18.5.1 Texas Instruments synchronous serial frame format
Interface pin
name/function
SPI
SCK
SSEL FS
MISO DR(M)
MOSI DX(M)
Figure 76
by the SSP module.
SSI
CLK
DX(S)
DR(S)
Microwire
SK
CS
SI(M)
SO(S)
SO(M)
SI(S)
shows the 4-wire Texas Instruments synchronous serial frame format supported
All information provided in this document is subject to legal disclaimers.
Pin Description
Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer
of data. It is driven by the master and received by the slave. When the SPI
interface is used, the clock is programmable to be active-high or active-low,
otherwise it is always active-high. SCK1 only switches during a data transfer.
Any other time, the SSPn interface either holds it in its inactive state, or does
not drive it (leaves it in high-impedance state).
Frame Sync/Slave Select. When the SSPn interface is a bus master, it
drives this signal to an active state before the start of serial data, and then
releases it to an inactive state after the serial data has been sent. The active
state of this signal can be high or low depending upon the selected bus and
mode. When the SSPn is a bus slave, this signal qualifies the presence of
data from the Master, according to the protocol in use.
When there is just one bus master and one bus slave, the Frame Sync or
Slave Select signal from the Master can be connected directly to the slave's
corresponding input. When there is more than one slave on the bus, further
qualification of their Frame Select/Slave Select inputs will typically be
necessary to prevent more than one slave from responding to a transfer.
Master In Slave Out. The MISO signal transfers serial data from the slave to
the master. When the SSPn is a slave, serial data is output on this signal.
When the SSPn is a master, it clocks in serial data from this signal. When the
SSPn is a slave and is not selected by FS/SSEL, it does not drive this signal
(leaves it in high-impedance state).
Master Out Slave In. The MOSI signal transfers serial data from the master
to the slave. When the SSPn is a master, it outputs serial data on this signal.
When the SSPn is a slave, it clocks in serial data from this signal.
Rev. 2 — 19 August 2010
Chapter 18: LPC17xx SSP0/1
UM10360
© NXP B.V. 2010. All rights reserved.
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