LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 586
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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31.1 Basic configuration
31.2 Introduction
31.3 Features
UM10360
User manual
The GPDMA is configured using the following registers:
The DMA controller allows peripheral-to memory, memory-to-peripheral, and
memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA
transfers for a single source and destination. For example, a bi-directional port requires
one stream for transmit and one for receives. The source and destination areas can each
be either a memory region or a peripheral.
1. Power: In the PCONP register
2. Clock: see
3. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
4. Programming: see
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UM10360
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Rev. 2 — 19 August 2010
Remark: On reset, the GPDMA is disabled (PCGPDMA = 0).
Enable register.
Eight DMA channels. Each channel can support an unidirectional transfer.
16 DMA request lines.
Memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers are
supported.
GPDMA supports the SSP, I2S, UART, A/D Converter, and D/A Converter peripherals.
DMA can also be triggered by a timer match condition. Memory-to-memory transfers
and transfers to or from GPIO are also supported.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority.
AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
Internal four-word FIFO per channel.
Supports 8-bit, 16-bit, and 32-bit wide transactions.
Table
All information provided in this document is subject to legal disclaimers.
38.
Rev. 2 — 19 August 2010
Section
31.6.
(Table
46), set bit PCGPDMA.
© NXP B.V. 2010. All rights reserved.
User manual
586 of 840
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