LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 402
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
17.4 Pin description
17.5 SPI data transfers
UM10360
User manual
Table 358. SPI pin description
Figure 74
are available with the SPI port. This timing diagram illustrates a single 8-bit data transfer.
The first thing you should notice in this timing diagram is that it is divided into three
horizontal parts. The first part describes the SCK and SSEL signals. The second part
describes the MOSI and MISO signals when the Clock Phase control bit (CPHA) in the
SPI Control Register is 0. The third part describes the MOSI and MISO signals when the
CPHA variable is 1.
In the first part of the timing diagram, note two points. First, the SPI is illustrated with the
Clock Polarity control bit (CPOL) in the SPI Control Register set to both 0 and 1. The
second point to note is the activation and de-activation of the SSEL signal. When
CPHA = 0, the SSEL signal will always go inactive between data transfers. This is not
guaranteed when CPHA = 1 (the signal can remain active).
Pin
Name
SCK
SSEL
MISO
MOSI
Type
Input/
Output
Input
Input/
Output
Input/
Output
is a timing diagram that illustrates the four different data transfer formats that
All information provided in this document is subject to legal disclaimers.
Pin Description
Serial Clock. The SPI clock signal (SCK) is used to synchronize the transfer of
data across the SPI interface. The SPI is always driven by the master and
received by the slave. The clock is programmable to be active high or active
low. The SPI is only active during a data transfer. Any other time, it is either in its
inactive state, or tri-stated.
Slave Select. The SPI slave select signal (SSEL) is an active low signal that
indicates which slave is currently selected to participate in a data transfer. Each
slave has its own unique slave select signal input. The SSEL must be low before
data transactions begin and normally stays low for the duration of the
transaction. If the SSEL signal goes high any time during a data transfer, the
transfer is considered to be aborted. In this event, the slave returns to idle, and
any data that was received is thrown away. There are no other indications of this
exception. This signal is not directly driven by the master. It could be driven by a
simple general purpose I/O under software control.
Master In Slave Out. The SPI Master In Slave Out signal (MISO) is a
unidirectional signal used to transfer serial data from an SPI slave to an SPI
master. When a device is a slave, serial data is output on this pin. When a
device is a master, serial data is input on this pin. When a slave device is not
selected, the slave drives the signal high-impedance.
Master Out Slave In. The SPI Master Out Slave In signal (MOSI) is a
unidirectional signal used to transfer serial data from an SPI master to an SPI
slave. When a device is a master, serial data is output on this pin. When a
device is a slave, serial data is input on this pin.
Rev. 2 — 19 August 2010
Chapter 17: LPC17xx SPI
UM10360
© NXP B.V. 2010. All rights reserved.
402 of 840
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