LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 612

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
31.6.5.1.1 Programming the DMA controller for scatter/gather DMA
31.6.5.1.2 Example of scatter/gather DMA
31.6.5.1 Linked list items
A Linked List Item (LLI) consists of four words. These words are organized in the following
order:
Note: The DMACCxConfig DMA channel Configuration Register is not part of the linked
list item.
To program the DMA Controller for scatter/gather DMA:
See
peripheral. The addresses of each LLI entry are given, in hexadecimal, at the left-hand
side of the figure. In this example, the LLIs describing the transfer are to be stored
contiguously from address 0x2002 0000, but they could be located anywhere. The right
side of the figure shows the memory containing the data to be transferred.
1. DMACCxSrcAddr.
2. DMACCxDestAddr.
3. DMACCxLLI.
4. DMACCxControl.
1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains
2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest
3. Write the first linked list item, previously written to memory, to the relevant channel in
4. Write the channel configuration information to the channel Configuration Register and
5. An interrupt can be generated at the end of each LLI depending on the Terminal
four words:
– Source address.
– Destination address.
– Pointer to next LLI.
– Control word.
The last LLI has its linked list word pointer set to 0.
priority and DMA channel 7 the lowest priority.
the DMA Controller.
set the Channel Enable bit. The DMA Controller then transfers the first and then
subsequent packets of data as each linked list item is loaded.
Count bit in the DMACCxControl Register. If this bit is set an interrupt is generated at
the end of the relevant LLI. The interrupt request must then be serviced and the
relevant bit in the DMACIntTCClear Register must be set to clear the interrupt.
Figure 135
All information provided in this document is subject to legal disclaimers.
for an example of an LLI. A section of memory is to be transferred to a
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
UM10360
© NXP B.V. 2010. All rights reserved.
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