LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 747

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 639.
[1]
[2]
[3]
[4]
[5]
UM10360
User manual
Exception
number
5
6
7-10
11
12-13
14
15
16 and above
To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than
interrupts. The IPSR returns the Exception number, see
See
See
See
Increasing in steps of 4.
Section 34.3.3.4
Section 34.4.3.9 “System Handler Priority
Section 34.4.2.7 “Interrupt Priority
[1]
Properties of the different exception types
34.3.3.3 Exception handlers
IRQ
number
-11
-10
-
-5
-
-2
-1
0 and above
for more information.
[1]
For an asynchronous exception, other than reset, the processor can execute another
instruction between when the exception is triggered and when the processor enters the
exception handler.
Privileged software can disable the exceptions that
configurable priority, see:
For more information about hard faults, memory management faults, bus faults, and
usage faults, see
The processor handles exceptions using:
•
•
•
•
•
Section 34.4.3.10 “System Handler Control and State Register”
Section 34.4.2.3 “Interrupt Clear-enable
Interrupt Service Routines (ISRs)
Interrupts IRQ0 and up are the exceptions handled by ISRs.
Fault handlers
Hard fault, memory management fault, usage fault, bus fault are fault exceptions
handled by the fault handlers.
System handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that
are handled by system handlers.
Exception
type
Bus fault
Usage fault
-
SVCall
-
PendSV
SysTick
Interrupt (IRQ)
Registers”.
All information provided in this document is subject to legal disclaimers.
Section
Registers”.
Rev. 2 — 19 August 2010
Configurable
Configurable
Configurable
Priority
Configurable
-
-
Configurable
Configurable
34.3.4.
Table
629.
[3]
[3]
[3]
[3]
[3]
[4]
Chapter 34: Appendix: Cortex-M3 user guide
Vector address
or offset
0x00000014
0x00000018
Reserved
0x0000002C
Reserved
0x00000038
0x0000003C
0x00000040 and above
Registers”.
[2]
Table 639
shows as having
[5]
Activation
Synchronous when
precise, asynchronous
when imprecise
Synchronous
-
Synchronous
-
Asynchronous
Asynchronous
Asynchronous
UM10360
© NXP B.V. 2010. All rights reserved.
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