LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 305

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 278: UARTn FIFO Control Register (U0FCR - address 0x4000 C008, U2FCR - 0x4009 8008, U3FCR -
UM10360
User manual
Bit
0
1
2
3
5:4
7:6
31:8
Symbol
FIFO Enable 0
RX FIFO
Reset
TX FIFO
Reset
DMA Mode
Select
-
RX Trigger
Level
-
0x4007 C008) bit description
14.4.6.1 DMA Operation
14.4.6 UARTn FIFO Control Register (U0FCR - 0x4000 C008, U2FCR -
Value Description
1
0
1
0
1
-
00
01
10
11
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the UnTHR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UARTn THR FIFO has held two or more characters at one time and
currently, the UnTHR is empty. The THRE interrupt is reset when a UnTHR write occurs or
a read of the UnIIR occurs and the THRE is the highest interrupt (UnIIR[3:1] = 001).
0x4009 8008, U3FCR - 0x4009 C008)
The write-only UnFCR controls the operation of the UARTn Rx and TX FIFOs.
The user can optionally operate the UART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an
affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register.
UART receiver DMA
In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character timeout occurs. See
the description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
UARTn FIFOs are disabled. Must not be used in the application.
Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access.
This bit must be set for proper UART operation. Any transition on this bit will
automatically clear the related UART FIFOs.
No impact on either of UARTn FIFOs.
Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the
pointer logic. This bit is self-clearing.
No impact on either of UARTn FIFOs.
Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the
pointer logic. This bit is self-clearing.
When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA
mode. See
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
These two bits determine how many receiver UARTn FIFO characters must be
written before an interrupt or DMA request is activated.
Trigger level 0 (1 character or 0x01)
Trigger level 1 (4 characters or 0x04)
Trigger level 2 (8 characters or 0x08)
Trigger level 3 (14 characters or 0x0E)
Reserved, user software should not write ones to reserved bits.
Section
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
14.4.6.1.
Chapter 14: LPC17xx UART0/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
0
0
0
NA
Reset Value
0
NA
0
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