LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 159
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
10.12.3 Receive Descriptor Base Address Register (RxDescriptor -
10.12.4 Receive Status Base Address Register (RxStatus - 0x5000 010C)
10.12.5 Receive Number of Descriptors Register (RxDescriptor - 0x5000 0110)
The status transitions from active to inactive if the channel is disabled by a software reset
of the Rx/TxEnable bit in the Command register and the channel has committed the status
and data of the current frame to memory. The status also transitions to inactive if the
transmit queue is empty or if the receive queue is full and status and data have been
committed to memory.
0x5000 0108)
The Receive Descriptor base address register (RxDescriptor) has an address of
0x5000 0108. Its bit definition is shown in
Table 150. Receive Descriptor Base Address register (RxDescriptor - address 0x5000 0108)
The receive descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of
descriptors.
The receive descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of
descriptors.
Table 151. receive Status Base Address register (RxStatus - address 0x5000 010C) bit
The receive status base address is a byte address aligned to a double word boundary i.e.
LSB 2:0 are fixed to “000”.
The Receive Number of Descriptors register (RxDescriptorNumber) has an address of
0x5000 0110. Its bit definition is shown in
Bit
1:0
31:2
Bit
2:0
31:3
•
•
•
It is enabled and the Rx/TxEnable bit is set in the Command register or it just got
disabled while still transmitting or receiving a frame.
Also, for the transmit channel, the transmit queue is not empty
i.e. ProduceIndex != ConsumeIndex.
Also, for the receive channel, the receive queue is not full
i.e. ProduceIndex != ConsumeIndex - 1.
Symbol
-
RxStatus
Symbol
-
RxDescriptor
bit description
description
All information provided in this document is subject to legal disclaimers.
Function
Fixed to ’000’
MSBs of receive status base address.
Rev. 2 — 19 August 2010
Function
Fixed to ’00’
MSBs of receive descriptor base address.
Table
Table
152.
150.
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
159 of 840
Reset
value
-
0x0
Reset
value
-
0x0
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