LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 252

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 250. Clear Buffer command bit description
11.13 USB device controller initialization
UM10360
User manual
Bit
0
7:1
Symbol Value Description
PO
-
11.12.14 Validate Buffer (Command: 0xFA, Data: none)
0
1
-
the SETUP data. If it is set then it should discard the previously read data, clear the PO bit
by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and
again check the status of the PO bit.
See
used.
When the CPU has written data into an IN buffer, software should issue a Validate Buffer
command. This tells hardware that the buffer is ready for sending on the USB bus.
Hardware will send the contents of the buffer when the next IN token packet is received.
Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the
Validate Buffer command and cleared when the data has been sent on the USB bus and
the buffer is empty.
A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet
Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP
packet. For the control endpoint the validated buffer will be invalidated when a SETUP
packet is received.
See
used.
The LPC17xx USB device controller initialization includes the following steps:
Packet over-written bit. This bit is only applicable to the control endpoint EP0.
The previously received packet is intact.
The previously received packet was over-written by a later SETUP packet.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
1. Enable the device controller by setting the PCUSB bit of PCONP.
2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk and
3. Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits
4. Enable the USB pin functions by writing to the corresponding PINSEL register.
5. Disable the pull-ups and pull-downs on the V
the desired frequency for cclk. For correct operation of synchronization logic in the
device controller, the minimum cclk frequency is 18 MHz. For the procedure for
determining the PLL setting and configuration, see
determining PLL0
in the USBClkCtrl register. Poll the respective clock bits in the USBClkSt register until
they are set.
PINMODE register by putting the pin in the “pin has neither pull-up nor pull-down
resistor enabled” mode. See
Section 11.14 “Slave mode operation”
Section 11.14 “Slave mode operation”
All information provided in this document is subject to legal disclaimers.
settings”.
Rev. 2 — 19 August 2010
Section 8.4 “Pin mode select register
Chapter 11: LPC17xx USB device controller
for a description of when this command is
for a description of when this command is
BUS
pin using the corresponding
Section 4.5.11 “Procedure for
UM10360
values”.
© NXP B.V. 2010. All rights reserved.
Reset value
0
NA
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