LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 461
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
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NXP Semiconductors
Table 401. Slave Transmitter mode
UM10360
User manual
I2CSTAT
Status
Code
0xA8
0xB0
0xB8
0xC0
0xC8
Status of the I
and hardware
Own SLA+R has been
received; ACK has
been returned.
Arbitration lost in
SLA+R/W as master;
Own SLA+R has been
received, ACK has
been returned.
Data byte in I2DAT has
been transmitted; ACK
has been received.
Data byte in I2DAT has
been transmitted; NOT
ACK has been
received.
Last data byte in
I2DAT has been
transmitted (AA = 0);
ACK has been
received.
2
C-bus
Application software response
To/From I2DAT
Load data byte or
Load data byte
Load data byte or
Load data byte
Load data byte or
Load data byte
No I2DAT action
or
No I2DAT action
or
No I2DAT action
or
No I2DAT action
No I2DAT action
or
No I2DAT action
or
No I2DAT action
or
No I2DAT action
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
To I2CON
STA STO SI
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AA
0
1
0
1
0
1
0
1
0
1
0
1
0
01
Next action taken by I
Last data byte will be transmitted and ACK
bit will be received.
Data byte will be transmitted; ACK will be
received.
Last data byte will be transmitted and ACK
bit will be received.
Data byte will be transmitted; ACK bit will
be received.
Last data byte will be transmitted and ACK
bit will be received.
Data byte will be transmitted; ACK bit will
be received.
Switched to not addressed SLV mode; no
recognition of own SLA or General Call
address.
Switched to not addressed SLV mode;
Own SLA will be recognized; General Call
address will be recognized if
I2ADR[0] = logic 1.
Switched to not addressed SLV mode; no
recognition of own SLA or General Call
address. A START condition will be
transmitted when the bus becomes free.
Switched to not addressed SLV mode;
Own SLA will be recognized; General Call
address will be recognized if
I2ADR[0] = logic 1. A START condition will
be transmitted when the bus becomes free.
Switched to not addressed SLV mode; no
recognition of own SLA or General Call
address.
Switched to not addressed SLV mode;
Own SLA will be recognized; General Call
address will be recognized if
I2ADR[0] = logic 1.
Switched to not addressed SLV mode; no
recognition of own SLA or General Call
address. A START condition will be
transmitted when the bus becomes free.
Switched to not addressed SLV mode;
Own SLA will be recognized; General Call
address will be recognized if
I2ADR.0 = logic 1. A START condition will
be transmitted when the bus becomes free.
Chapter 19: LPC17xx I2C0/1/2
UM10360
2
© NXP B.V. 2010. All rights reserved.
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