LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 604

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 563. DMA channel control registers (DMACCxControl - 0x5000 41xC)
UM10360
User manual
Bit
26
27
28
29
30
31
Name
SI
DI
Prot1
Prot2
Prot3
I
31.5.21 DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0)
Function
Source increment:
0 - the source address is not incremented after each transfer.
1 - the source address is incremented after each transfer.
Destination increment:
0 - the destination address is not incremented after each transfer.
1 - the destination address is incremented after each transfer.
This is provided to the peripheral during a DMA bus access and indicates that the access is in user
mode or privileged mode. This information is not used in the LPC17xx.
0 - access is in user mode.
1 - access is in privileged mode.
This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the
access is bufferable or not bufferable. This information is not used in the LPC17xx.
0 - access is not bufferable.
1 - access is bufferable.
This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the
access is cacheable or not cacheable. This information is not used in the LPC17xx.
0 - access is not cacheable.
1 - access is cacheable.
Terminal count interrupt enable bit.
0 - the terminal count interrupt is disabled.
1 - the terminal count interrupt is enabled.
The eight DMACCxConfig Registers (DMACC0Config to DMACC7Config) are read/write
with the exception of bit[17] which is read-only. These registers configure each DMA
channel. The registers are not updated when a new LLI is requested.
bit assignments of the DMACCxConfig Register.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
…continued
Table 564
UM10360
© NXP B.V. 2010. All rights reserved.
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