LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 780

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
Table 670. UFSR bit assignments
Remark: The UFSR bits are sticky. This means as one or more fault occurs, the
associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit,
or by a reset.
Bits
[15:10]
[9]
[8]
[7:4]
[3]
[2]
[1]
[0]
Name
-
DIVBYZERO
UNALIGNED
-
NOCP
INVPC
INVSTATE
UNDEFINSTR Undefined instruction usage fault:
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
Reserved.
Divide by zero usage fault:
0 = no divide by zero fault, or divide by zero trapping not enabled
1 = the processor has executed an SDIV or UDIV instruction with a divisor
of 0.
When the processor sets this bit to 1, the PC value stacked for the
exception return points to the instruction that performed the divide by
zero.
Enable trapping of divide by zero by setting the DIV_0_TRP bit in the
CCR to 1, see
Unaligned access usage fault:
0 = no unaligned access fault, or unaligned access trapping not enabled
1 = the processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP
bit in the CCR to 1, see
Unaligned LDM , STM , LDRD , and STRD instructions always fault irrespective
of the setting of UNALIGN_TRP.
Reserved.
No coprocessor usage fault. The processor does not support
coprocessor instructions:
0 = no usage fault caused by attempting to access a coprocessor
1 = the processor has attempted to access a coprocessor.
Invalid PC load usage fault, caused by an invalid PC load by
EXC_RETURN:
0 = no invalid PC load usage fault
1 = the processor has attempted an illegal load of EXC_RETURN to the
PC, as a result of an invalid context, or an invalid EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return
points to the instruction that tried to perform the illegal load of the PC.
Invalid state usage fault:
0 = no invalid state usage fault
1 = the processor has attempted to execute an instruction that makes
illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return
points to the instruction that attempted the illegal use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
0 = no undefined instruction usage fault
1 = the processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return
points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
Table
Chapter 34: Appendix: Cortex-M3 user guide
662.
Table
662.
UM10360
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