EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 99

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EZ80F91MCU

Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
eZ80F91 MCU
Product Specification
80
Z80 bus mode Read and Write timing is illustrated in Figures 9 and 10 . The Z80
bus mode states can be configured for 1 to 15 CPU system clock cycles. In the
figures, each Z80 bus mode state is two CPU system clock cycles in duration. Fig-
ures 9 and 10 also illustrate the assertion of 1 wait state (T
) by the external
WAIT
peripheral during each Z80 bus mode cycle.
T1
T2
T
T3
CLK
System Clock
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
Figure 9. Example: Z80 Bus Mode Read Timing
PS019209-0504
P R E L I M I N A R Y
Chip Selects and Wait States

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