EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 84
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EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 84 of 396
- Download datasheet (5Mb)
Interrupt Controller
PS019209-0504
Maskable Interrupts
The interrupt controller on the eZ80F91 device routes the interrupt request signals
from the internal peripherals, external devices (via the internal port I/O), and the
nonmaskable interrupt (NMI) pin to the CPU.
On the eZ80F91 device, all maskable interrupts use the CPU’s vectored interrupt
function. The size of the I register is modified to 16 bits in the eZ80F91 device, dif-
fering from that of previous versions of the eZ80
of interrupt vector table placement. Additionally, the size of the IVECT register is
increased from 8 bits to 9 bits to provide an interrupt vector table that can be
expanded and is more easily integrated with other interrupts.
The vectors are 4 bytes (32 bits) apart, even though only 3 bytes (24 bits) are
required. A fourth byte is implemented for both programmability and expansion
purposes.
Starting the interrupt vectors at
controller vectors with the RST vectors. Table 11 lists the low-byte vector for each
of the maskable interrupt sources. The maskable interrupt sources are listed in
order of their priority, with vector
mode, the full 24-bit interrupt vector is located at starting address {I[15:1],
IVECT[8:0]}, where I[15:0] is the CPU’s Interrupt Page Address Register.
Table 11. Interrupt Vector Sources by Priority
Note: *The vector addresses 064h and 068h are left unused to avoid conflict with the nonmaskable
Priority
0
1
2
3
4
5
6
7
8
interrupt (NMI) address 066h. The NMI is prioritized higher than all maskable interrupts.
Vector
04Ch
05Ch
040h
044h
048h
050h
054h
058h
060h
EMAC SYS
P R E L I M I N A R Y
EMAC Rx
EMAC Tx
Source
Timer 0
Timer 1
Timer 2
Timer 3
Flash
PLL
40h
40h
allows for easy implementation of the interrupt
being the highest-priority interrupt. In ADL
Priority
®
24
25
26
27
28
29
30
31
32
CPU, to allow for a 16 MB range
Vector
0ACh
0BCh
0C0h
0A0h
0A4h
0A8h
0B0h
0B4h
0B8h
Product Specification
Interrupt Controller
eZ80F91 MCU
Port B 0
Port B 1
Port B 2
Port B 3
Port B 4
Port B 5
Port B 6
Port B 7
Port C 0
Source
65
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