EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 264
EZ80F91MCU
Manufacturer Part Number
EZ80F91MCU
Description
eZ80Acclaim-TM Flash Microcontrollers
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.EZ80F91MCU.pdf
(396 pages)
- Current page: 264 of 396
- Download datasheet (5Mb)
PS019209-0504
EMAC Shared Memory Organization
Internal Ethernet SRAM shares memory with the CPU. This memory is divided
into the Transmit buffer and the Receive buffer by defining three registers, as
listed below.
•
•
•
This internal Ethernet shared memory is depicted in Figure 48.
Figure 48. internal Ethernet Shared Memory
The Transmit and Receive buffers are able to be subdivided into packet buffers of
32, 64, 128, or 256 bytes in size. The packet buffer size is set in bits 7 and 6 of the
EmacBufSize register. An Ethernet packet can accommodate multiple packet buff-
ers. At the start of each packet is a descriptor table that describes the packet.
Each actual Ethernet packet follows the descriptor table, as illustrated in
Figure 49.
RHBP
TLBP
BP
Transmit Lower Boundary Pointer (TLBP)—this register points to the start of
the Transmit buffer in the internal Ethernet shared memory space
Boundary Pointer (BP)—this register points to the start of the Receive buffer
Receive High Boundary Pointer (RHBP)—this register points to the end of the
Receive buffer + 1
Rx Buffer
Tx Buffer
P R E L I M I N A R Y
Ethernet Media Access Controller
Product Specification
eZ80F91 MCU
245
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