EZ80F91MCU ZILOG [Zilog, Inc.], EZ80F91MCU Datasheet - Page 86

• Manufacturer Part Number: EZ80F91MCU
• Description: eZ80Acclaim-TM Flash Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Table 12. Vectored Interrupt Operation
PS019209-0504
Memory
Mode
Z80 Mode
ADL Mode
Note:
ADL
Bit
0
1
device is explained in Table 12. Interrupt sources are required to be active until
the interrupt service routine (ISR) starts.
The lower bit of the I register is replaced with the MSB of the IVECT from the inter-
rupt controller. As a result, the interrupt vector table is required to be placed onto a
512-byte boundary. Setting the LSB of the I register produces no effect on the
interrupt vector address.
MADL
Bit
0
0
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [8:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [8:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
IEF1
IEF2
The Starting Program Counter is effectively {MBASE, PC[15:0]}.
Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack.
The ADL mode bit remains cleared to 0.
The interrupt vector address is located at { MBASE, I[7:1], IVECT[8:0] }.
PC[23:0]
The interrupt service routine must end with RETI.
IEF1
IEF2
The Starting Program Counter is PC[23:0].
Push the 3-byte return address, PC[23:0], onto the SPL stack.
The ADL mode bit remains set to 1.
The interrupt vector address is located at { I[15:1], IVECT[8:0] }.
PC[23:0]
The interrupt service routine must end with RETI.
0
0
0
0
( { MBASE, I[7:1], IVECT[8:0] } ).
( { I[15:1], IVECT[8:0] } ).
P R E L I M I N A R Y
Product Specification
Interrupt Controller
eZ80F91 MCU
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